Zero ASIC Wants to "Democratize Chip Making" with a Zero-Code, LEGO-Like ASIC Design Platform

Company aims for a hundredfold reduction in the cost to getting your own custom system-in-package (SIP) designed and manufactured.

Gareth Halfacree
7 months agoFPGAs / HW101

Cambridge-based fabless semiconductor startup Zero ASIC has announced early access for its ChipMaker platform, by which it aims to "democratize chip making" — by providing a LEGO-like no-code environment to build your own custom chips at a hundredfold reduction in cost.

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," claims Zero ASIC founder and chief executive officer Andreas Olofsson of the problem his company has set out to solve. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

The core of Zero ASIC's offering is ChipMaker, a platform which aims to make custom chip design accessible to all. Rather than expecting a designer to start from scratch, ChipMaker provides a library of proven designs known as "eBricks" — to be assembled LEGO-like into a finished system-in-package (SIP) with exactly the features required. As designed are built, they can be tested on cloud-connected field-programmable gate arrays (FPGAs) before the final design is submitted for manufacturing.

These "eBrick" chiplets include a quad-core dual-issue RISC-V application-class processor capable of running Linux, an embedded FPGA (eFPGA) with 5k look-up tables (LUTs), 3MB of static RAM (SRAM), and a three tera-operations per second (TOPS) machine learning accelerator, Zero ASIC explains. These are then connected using a grid-like 3D interposer dubbed "eFabric" which includes 512Gb/s/mm of on-fabric bisection bandwidth and 128Gb/s/mm of 2D chiplet bandwidth — or 128Gb/s/mm² for 3D chiplets.

ChipMaker is now available for early access on the Zero ASIC website, though physical chips won't be sampling until the third quarter of 2024; the company has also announced that it is giving live demonstrations of the ChipMaker platform at the Open Compute Global Summit until October 19.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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