This 4,096-Spin Annealing Processor Could Deliver Quantum-Beating Performance with Minimal Power

New processor design is claimed to be more than 2,000 times as energy efficient for combinatorial optimization than traditional PCs.

Gareth Halfacree
28 days agoSustainability / HW101 / FPGAs

Researchers from the Tokyo University of Science have developed a new, scalable processor design that can deliver a "remarkable speed-up" for real-world problem-solving operations — which, they say, could outperform traditional computers in power efficiency by three orders of magnitude.

"We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing preprocessing at the edge for the cloud," Takayuki Kawahara, professor and project lead, explains of the team's work and the earlier efforts on which it builds. "Using the unique processing architecture announced by the Tokyo University of Science in 2020, we have realized a fully coupled LSI (Large Scale Integration) on one chip using 28nm CMOS technology. Furthermore, we devised a scalable method with parallel-operating chips, and demonstrated its feasibility using FPGAs (Field-Programmable Gate Arrays) in 2022."

A novel, scalable processor design could deliver quantum-like computational performance at the edge, researchers claim. (📹: Tokyo University of Science)

The architecture in question is designed to deliver energy-efficient yet high-performance annealing computation for combinatorial optimization problems — going toe-to-toe with quantum computers in a fraction of the power demand. Previous efforts have proven the concept, but the complexity of the chips has made it hard to scale from a small proof-of-concept to a larger implementation that could offer real-world advantages.

In the team's latest work 36 CMOS chips are used in parallel with one controlling FPGA — enough to use a spin-thread method to execute eight solution searches in parallel across 4,096 spins. This parallel processing combined with a new technique to cut the power draw of the system in half delivers some impressive energy efficiency figures: 2.9W total power draw for 10MHz operation while solving a vertex cover problem.

This, the researchers claim, represents a major gain in efficiency: compared to simulating the same system on a standard desktop PC, the annealing processor delivered a power-performance ratio some 2,306 times higher — and a straight computation speed boost of 34×.

"In the future, we will develop this technology for a joint research effort targeting an LSI system with the computing power of a 2050-level quantum computer for solving combinatorial optimization problems," Kawahara claims. "The goal is to achieve this without the need for air conditioning, large equipment, or cloud infrastructure, using current semiconductor processes. Specifically, we would like to achieve 2 million spins by 2030 and explore the creation of new digital industries using this."

The team's work has been published in the journal IEEE Access under open-access terms.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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