The ButterStick Is a Powerful Platform for Prototyping with the Lattice Semiconductor ECP5
Greg Davill's latest hand-assembled PCB, the ButterStick, makes my work look like I'm all butterfingers!
You really have to hand it to Greg Davill.
So rarely do we see a "lash-up," or even something we'd consider a "prototype" from him.
Indeed, even his "bodges" are work that would make most of us think twice before attempting ourselves!
One of his latest works, the ButterStick (that's 118ml of butter, for those of us on metric units) touts itself as an exploration into the high-speed world of LVDS interfaces, alongside the capabilities of the Lattice Semiconductor ECP5 FPGA.
Looking like a polished product in itself — again, no surprises there for Davill — the ButterStick is a serious bit of kit, targeting some serious interface speeds.
Beyond the ECP5 itself, the ButterStick is packing some hefty peripherals in its feature list — let's take a little look at the loadout here.
First and foremost, you might notice the rather prominent RJ45 connector on the righthand side of the board.
You could be forgiven for thinking "Ethernet? No big deal, most of my SBCs are sporting that" — but the LEDs, lovingly laid out above the connector reveal a hidden feature of this interface — it's full-on Gigabit Ethernet! That's a hefty data rate for getting data in and out of this board — over longer distances than perhaps the LVDS interfaces would allow for.
These phenomenal speeds are achieved by wiring the ECP5 directly to a Microchip KSZ9031, triple-speed Ethernet PHY. This is a great part to play with, with all sorts of nifty features — from on-chip termination resistors for the differential pairs of the connection, to the LinkMD® features, which allow for Time Domain Reflectometry cable fault detection, all from the same single chip. Having the ability to estimate the distance until a cable fault, by measuring the reflected electronic signal, without the need for additional instrumentation — that's very cool!
With the GigE handling the high-level data interface to the ButterStick, we can now turn our attention to the LVDS interfaces. LVDS (Low Voltage Differential Signaling) can get you some pretty fast interface data rates, provided you can maintain the signal integrity needed to maintain that finely balanced eye-diagram, used while tuning the connection hardware.
You can gain access to those signals by connecting to the ButterStick using one of the three "SYZYGY-compatible" connectors.
SYZYGY? Clean your keyboard out, Tom!
Fun trivia — Syzygy was a new word for me today — it has meaning in astronomy to indicate a rough, straight line configuration of three or more celestial bodies.
That kind of makes sense in terms of a connector — many I/O in a straight line configuration. It's not so much an acronym as a related term, and works well for the name of this relatively new standard.
The SYZYGY-compatible connectors have found their way into a number of physical interfaces for various high-speed FPGA boards, as can be seen below, with the Opal Kelly Brain-1 board as an example.
While Opal Kelly actually maintain the SYZYGY standard, they have made it free to license on other boards, by other manufacturers — making it a workable standard for the OSHW (and less open, too) high-speed hardware worlds
Think of the connector as a happy half-way house, sitting in between the Digilent PMOD standard, and the beast that is the VITA 57.1 FMC (FPGA Mezzanine Card) standard connector.
The PMOD is a lovely, low-cost interface, that is implemented using a simple 0.1" box header. Great for a seven-segment display, but useless for anything like LVDS, or impedance controlled signals.
The FMC connector allows for the other end of the extreme, with a performance that is hard to match with other connectors — supporting LVDS at many Gbps — but with an associated price tag that is as high as you might imagine. See those two connectors at the top of this Kintex card below? They are FMC.
Price aside, merely breaking out the full complement of pins available on such a connector is no small feat itself, so the SYZYGY standard sits nicely in between the two existing standards, not only in price, but in I/O count and capability.
As implemented, we can see that the SYZYGY interface allows for 12 single-ended signals, eight(!) differential pairs, and two high-speed differential clock signals.
The two I2C ports we can see on the right hand side of the connector allow for configuration EEPROMS on the extension card, and what I can only tease out to be communications with a Microchip ATmega328, seemingly implemented as a PMIC — enabling and sequencing power enable signals to the different SYZYGY headers as needed.
Perhaps we can infer some more detail on the operation from checking out other parts of the schematic.. Let's have a look at the power supplies to the SYZYGY ports... Ah yes, here we go...
It appears that each SYZYGY port also features the ability to dial in the supply voltage required by the peripheral card that is plugged into it.
The rather neat arrangement of the SOT23-5 and SOT23-6 parts we see adjacent to each of the SYZYGY ports is a combination of a Texas Instruments DAC081, in conjunction with a TI TPS73101 adjustable voltage regulator.
And here, we see where the PMIC I2C bus ends up. By writing a different control bytes to the output register of the DAC801, we see that the output voltage of the TPS73101 will be adjusted, due to the difference in voltage observed on the FB pin of the regulator.
This section of the schematic alone should get tucked away in your scrapbook of implementations, as it looks like a solid base from which to design an adjustable power supply. As laid out, it's pretty easy to follow, and derive your own work from — as needed!
Feel the power of the D̶a̶r̶k̶ ̶S̶i̶d̶e̶ robust PSU implementation!
FPGAs are notoriously power-hungry beasts, and when you're looking at the more capable end of the spectrum of parts, well, the power budget of your design quickly becomes a critical factor of whether or not the project will function reliably.
It's worth taking a look at the ButterStick implementation, as it's a well laid out reference for other such power-hungry, multi-rail designs.
Starting at the top left of this schematic page, we first encounter the LTC4367 from Analog Devices — which is the second line of defense in protecting this rather pricey PCBA from the late night coding sessions, and the fumbled hardware connections that some of us might make under such conditions!
(If you're querying the part number, thinking that looks like another MFG... Well, recall the merger? I still forget on some days...)
The idea of erroneously connecting the power to this painstakingly handcrafted PCB must have caused Davill some lost sleep — as not only do we have a polarized power input connector — the first line of defense against such mistakes, but directly after that, we have the LTC4367, which is an all-in-one chip to protect against undervoltage, overvoltage, and reverse polarity on the input voltage to the board.
Once the LTC4367 has decided that we've got something reasonable connected to the board power input terminals, it drives the AON7804 dual N-FET, in order to pass the voltage input along to the next device in the power supply scheme, a TI TPS542951 switching regulator.
The eagle-eyed will notice a certain symmetry to the layout of this schematic part — and the dual inductors are a pretty good indicator that this is a dual rail / dual output part — capable of supplying 2A of current on the primary channel (5V in this case), and 3A on the secondary channel (here, that's 3.3V).
We mentioned that FPGAs can take a lot of current, so the decision to use a switching DC/DC regulator makes sense — any LDO passing current up at those levels will have quite the thermal load to dissipate into the board, which is just needlessly wasting energy.
They are OK for smaller differences in input voltage w.r.t output voltage, but dropping 12V, for example, down to the 2V5, 1V8 and even 1V1 rails required by the FPGA core and I/O will generate a lot of heat in doing so.
A well-designed switcher is able to more efficiently meet such current demands and these days, switching frequencies (700 kHz for the TPS542951) have minimal impact on a well filtered power stage.
Finally, we look at the last stages of the power scheme.
The 1V1 rail is supplied by a Torex XCL206B123, which is one of the recent trend of "micro" DC-DC converters that various MFG are now offering.
While from the top view, this looks like a simple surface mount inductor, these tiny packages are full DC-DC converters, and while we normally see integrated controllers with in-package switching elements (converters), now we are starting to see full DC-DC converters, with the requisite inductor being incorporated into the converter package itself!
It's very clever stuff, and makes laying out the high-current switching paths and traces something of days gone by!
With the XCL206 able to pass 600mA to its output, the remaining current capability of the primary TPS542951 regulator is left to serve the variable power supplies of the SYZYGY connectors that we discussed earlier.
The slightly less demanding requirements of the 2V5 and 1V8 rails are met by a pair of TLV725P and TLV718P LDO regulators, each packaged as ridiculously tiny 1mm x 1mm X2SON packages.
The photo below shows these regulators mid placement on one of the OrangeCrab boards — don't let the blue solder mask fool you otherwise!
The above photo maybe doesn't do justice to the scale of these parts...
Yeah, these things are the sort of part that would happily disappear across the room if you were to sneeze a the wrong moment. That's the sort of fun I want in a board build.
So, we've covered the power scheme of this board — almost exhaustively! I feel that is meritied however, as a good power supply is critical to the operation of many FPGA designs.
They have sharp current spikes and a usually non-trivial base current consumption, depending on the bitstream loaded and the speed at which clocked.
So what else is there to reflect on here? What other tips and tricks are tucked away in the hardware design for the ButterStick?
Heaps of HyperRAM
With so much potential data streaming in and out of the ButterStick, the hefty ECP5 will need some working memory to handle it's operations and intermediate data storage.
As with all memory, there is usually a tradeoff between the two extremes of the implementation.
Most of us have used an I2C or SPI EEPROM before. Cheap, simple, and easy to implement are all qualities you and I favor.
In the context of the speeds and data rates of an FPGA, they are pretty useless here as anything much more than configuration memories.
At the other end of the memory pool are things like RAM, with parallel interfaces and outrageous clock speeds, these memories are able to offer read and write cycles that are more in line with the speeds that FPGAs can be clocked at!
Thing is, those high-speed parallel interfaces are usually incredibly taxing to lay out and implement. Not to mention that depending on the level of integration of your memory, you might also be looking at taking on the controller functions yourself — certain memories need refreshing (they are volatile), and also, they can be much more expensive than other memory types.
A recent range of parts to join the selection tables of Digikey, Mouser, et al, is the HyperRAM, from Cypress. With a I/O interface that sits physically somewhere between conventional RAM and other, more integrated memories, this new memory interface and bus can offer advantages from both sides of the fence, and can also be paired with HyperFLASH memories, all sitting on the same bus.
We can see that the Davill has implemented a dual HyperBUS interface on his ECP5, allowing for two IS66WVH16M8ALL parts on board — for a total of 256Mbit of SRAM.
While HyperRAM might be all the rage, we still have a need for one of those SPI FLASH parts we talked about earlier, in order to hold the FPGA configuration bitstream. Below, we can see the QSPI interface of the ECP5.
These signals are mapped to a S25FL127S, 128Mbit QSPI FLASH memory, from Cypress. 128Mbit worksout at a whopping 16MB of storage, which in addition to storing the most complex of bitstreams for the FPGA, leaves quite a lot of spare room for user storage too!
Go and get stuck in to the ButterStick!
I could happily pick apart designs like these for days, and no doubt will continue to happily do so for some time yet. However, you, dear reader, don't have all day to sit and read my ramblings.
We are really lucky to have people like Davill turning out hardware designs of this level of complexity and thought, openly, for us to all learn from, and the ButterStick is no exception.
With every aspect of the project up for grabs, from the schematic, to hardware, to firmware and gateware required to kick the hardware into life, it's all there on Davill's GitHub repo for the ButterStick.
If you are looking to learn a few reference implementations that have been proven already, or just want to see what goes into the layout and routing of these designs, this is a goldmine of information to learn from.
What's more, following along with Davill on Twitter can often provide some "fly on the wall" insight into his design process, he's not afraid to share his tricks for our benefit.
The ButterStick will be coming to GroupGets as part of the Hackster Launch program. Sign up to get notified of when Davill's campaign is live!