RISC-V Ratifies New Specifications, Including a "Cheap" Multiply-Only Operation for MCUs and FPGAs

New Zmmul extension targets microcontrollers and "simple FPGA soft cores," which do a lot of multiplying but little to no division.

Gareth Halfacree
5 days agoHW101 / Debugging

RISC-V International has announced a new batch of specifications detailing extensions and standards, which can be added to the RISC-V instruction set architecture — the first to be ratified so far this year.

"These new specifications accelerate embedded and large-system design," explains RISC-V International chief technical officer Mark Himelstein. "Debugging is one of the hardest things to do on a chip. E-Trace for RISC-V creates a standard way to do processor trace that’s extremely efficient and is especially useful in embedded system design."

The aforementioned E-Trace specification, which defines a high-efficiency method for processor tracing complete with specified signals and a compressed branch trace algorithm, is only the first of the four specifications RISC-V International has formally ratified — adding to the 16, representing over 40 individual extensions, ratified last year.

The second ratified specification is the RISC-V Supervisor Binary Interface (SBI), a firmware layer between hardware and the operating kernel that offers a supervisor-mode application binary interface. With the SBI specification, it's hoped that it will be easier to provide common platform services across all RISC-V-compatible operating systems.

The third specification, RISC-V Unified Extensible Firmware Interface (UEFI) Protocols are likewise aimed at improving compatibility — this time by bringing the existing UEFI standards, common in mainstream computing, to RISC-V. Finally, the Zmmul Multiply Only extension has been added to the RISC-V Unprivileged Specification as a way to offer a low-cost solution to workloads featuring heavy multiplication but little to no division.

"For many microcontroller applications, division operations are too infrequent to justify the cost of divider hardware," explains Himelstein of the extension's benefit. "The RISC-V Zmmul extension will benefit simple FPGA soft cores in particular."

"The RISC-V culture of contribution and collaboration continues to produce impressive and strategic results," claims Calista Redmond, RISC-V International chief executive. "RISC-V members are leaders in the era of open compute, proving that collaboration accelerates innovation through shared investment while growing global opportunity."

The ratified specifications were announced today at Embedded World and are live now on the RISC-V Non-ISA Specifications and RISC-V ISA Specifications GitHub repositories now.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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