Open Source RSD Soft-Core Processor Offers 2.5x Performance Boost Over Rival Out-of-Order Designs
Optimised to boost performance and preserve FPGA resources, RSD is claimed to be head and shoulders above the competition.
A team of developers led by Susumu Mashimo at Kyushu University, the University of Tokyo, Nagoya University, and the National Institute of Informatics, Japan, have released a paper and source code for an open source out-of-order RISC-V soft core processor which, they claim, is optimized for implementation on a field-programmable gate array: RSD.
"High-performance soft processors in field-programmable gate arrays (FPGAs) have become increasingly important as recent large FPGA systems have relied on soft processors to run many complex workloads, like a network software stack," Mashimo's team explains in the abstract to the RSD paper. "An out-of-order (OoO) superscalar approach is a good candidate to improve performance in such cases, as evidenced from OoO hard processor studies. Recent studies have revealed, however, that conventional OoO processor components do not fit well in an FPGA, and it is thus important to carefully design such components for FPGA characteristics.
"Hence, we propose the RSD processor: a new, open source OoO RISC-V soft processor optimized for an FPGA. The RSD supports many aggressive OoO execution features, like speculative scheduling, OoO memory instruction execution and disambiguation, a memory dependence predictor, and a non-blocking cache. While the RSD supports such aggressive features,it also leverages FPGA characteristics. Therefore, it consumes fewer FPGA resources than are consumed by existing OoO soft processors, which do not support such aggressive features well."
According to the team's internal testing, those optimizations are easily measurable: Benchmarks have shown the RSD core achieving up to a 2.5-fold performance boost in the Dhrystone benchmark while using 60 percent fewer registers and 64 percent fewer lookup tables (LUTs) on the FPGA compared to current state-of-the-art open source out-of-order designs.
RSD itself is written in SystemVerilog and designed to run on a Xilinx Zynq FPGA development board — though could be ported to other devices, thanks to its permissive Apache Licence 2.0. Based on the RVM32IM 32-bit RISC-V instruction set architecture, with support for native and Zephyr applications, the design includes a two-fetch front-end and five-issue back-end pipelines with up to 64 in-flight instructions — all of which is configurable.
The team's paper, which was presented at the International Conference on Field Programmable Technology 2019 (FPT 2019), is available from the University of Tokyo under open-access terms; the source code for RSD, meanwhile, can be found on the project's GitHub repository.