The use of soft processors within an FPGA to provide certain functionalities that can't be feasibly be performed in HDL (hardware description language) has become a staple in the world of FPGA design. Given the rise of FPGAs used for applications such as hardware acceleration for massively parallel computing structures, and the expectation for them to interface with more complex systems or integrate easily into existing systems, it's almost necessary for most FPGA designs to implement some sort of CPU-like processor via logic synthesis.
While there are many 32-bit options (probably the majority of what's on the market) and a substantial amount of extremely resource-optimized 8-bit soft processors out there, there is a gap that has developed in the middle with a lack of options for 16-bit soft processors. Stephan Nolting decided to address this gap with his ground up implementation of an MSP430 tiny microcontroller-like processor system.
The MSP430 is a popular choice in the microcontroller world due to its ultra-low power consumption and broad range of available versions for virtually any application or design need. The MSP430 contains a RISC-based CPU with ISP (in-system programmable) flash, up to 100 I/O, digital and analog peripheral resources, and embedded emulation capabilities.
All of the MSP430's popularity in the microcontroller world translates well into the soft processor and FPGA world, particularly its ultra low power consumption characteristics since one of the biggest challenges in FPGA design is optimization for low power and battery powered applications.
While the NEO430 is MSP430 compatible and provides compatibility with the original instruction set, the implemented modules of the NEO430 are completely different and the resulting address space layout are new. The NEO430 boasts standard features such as a timer, watchdog, UART, TWI and SPI serial interfaces, general purpose IO ports, an internal bootloader and internal memory for program code and data. Part of the brilliance on the NEO430 processor is that all of the peripheral modules are optional. If you do not need them for a particular design, they can simply be excluded from implementation within the FPGA to reduce the footprint of the system. As a further added bonus, the NEO430's Wishbone bus gives you the option to add your own custom modules to the system. This is the perfect hook to pass data back and forth between the NEO430 processor and the rest of the HDL logic in the FPGA to give you the full system on chip (SoC) design.
To develop higher level software on the NEO430, the existing open-source msp430-gcc C/C++ compiler toolchain from TI can be used to create custom applications on the NEO430. The MSP430 GCC compiler toolchain has Windows, Linux, and MacOS versions available. While the NEO430 datasheet only walks through Windows Powershell and Linux software setup, the main steps overall include: install the MSP430 GCC toolchain, clone the NEO430 repository to a local folder on the host system, add the MSP430 to the system path, and compile the project source files using make. If you really wanted to, the software side for NEO430 could be developed on MacOS, but as for the hardware side of compiling the NEO430's HDL into a bitstream for the FPGA, that would need to be done in Windows or Linux as there is currently no FPGA EDA tool available on MacOS.
As for the hardware implementation of the NEO430, all that needs to be done is to create a new project in your FPGA EDA of choice and make a reference to the HDL files as a new library, then instantiate an instance of the NEO430 top file. A test bench is included in the repository that can be used as either a traditional test bench or as a substitute top level design if you don't have a design in mind yet and you're just looking to check out the NEO430.
Some of the key differences to note of the NEO430 compared to it's inspirational counterpart, the MSP430, include:
- The max 48KB instruction and 12KB data memory page sizes compared to the max 64KB memory page sizes in the MSP430.
- No support for decimal place arithmetic (DADD) operations.
- The NEO430 works from a single clock domain for the entire processor.
- There is only one power-down (sleep) mode.
- The NEO430's tool chain (makefiles, boot-code and linker script) required for application compilation are fully custom to it.
The table above gives and idea of how much programmable logic resources the default implementation of the NEO430 uses in the mid-range sized FPGAs from the main vendors Xilinx, Intel/Altera, and Lattice Semiconductor. The Lattice iCE FPGAs are smaller in logic size compared to its Xilinx and Intel counterparts, but the NEO430 still fits nicely with a bit of optimization. Again, because all of the peripherals are defined at instantiation in the HDL project, it is very easy to customize the NEO430 to fit just about any FPGA chip you need it on.
Overall, this is just scratching the surface of the cool features the NEO430. Check out the projec's GitHub for a full getting started guide and detailed features lists.