There's a new world record in the semiconductor field: 6,000 RISC-V cores crammed into a single field-programmable gate array (FPGA), as measured by the CoreScore benchmark.
"What do you do when you have the award-winning SERV, the world's smallest RISC-V CPU," asks Olof Kindgren, creator of the SERV core and the CoreScore benchmark that measures just how many of the tiny cores you can cram into a chip. "Well, among other things we of course want to see how many SERV cores you can fit into various devices. This is what CoreScore is for. And on top of that list of currently 30 boards we can now find Sylvain Lefebvre and his Xilinx VCU128 board that fits 6000 SERV cores."
The target development board, built around a Xilinx Virtex UltraScale+ VCU128 FPGA, is the first to have broken 6,000 of the RISC-V cores — heading to the top of the CoreScore benchmark table, ahead the previous-best 5,087 cores on a Xilinx VCU118.
It's an impressive achievement, though one which is designed to showcase the capacity of an FPGA and the efficiency of the placing and routing tools available to the developer than anything else: The bit-serial SERV core is designed to be as small as possible at the cost of functionality, and isn't the sort of thing you'd run the Linux kernel — or 6,000 Linux kernels - on.
"We are nearing the max," Lefebvre says of his 6,000-core record, "with 98.5% LUTs [Lookup Tables] (and 100% BRAM [Block RAM]) of the VCU128 #fpga utilized. It's been great fun working with Olof Kindgren on this, and it was a perfect intro to our Xilinx VCU128 Monster."
Anyone interested in trying out the CoreScore benchmark themselves can find the current entries on the official website and the source code on GitHub under the permissive Apache 2.0 license; SERV itself is also on GitHub under the permissive MIT-equivalent ISC license.