Since the first instalment of this blog now five years ago (30/9/2013), we have experienced Xilinx’s transformation from an FPGA company at the beginning of the Zynq 7000 series journey into the platform company it is now.
That journey has taken us from FPGA to the first SoC in the Zynq 7000, to the MPSoC and RFSoC, and now to ACAP.
Versal, if I remember correctly, is a name fused from the Versatility and Universality and will be available in six portfolios each with an application optimized offering:
- Versal AI Core — Offering the maximum number of intelligent engines.
- Versal AI Edge — Efficient intelligent engine, targeted to meet tight thermal constraints.
- Versal AI RF — Multi-gigasample per second ADC and DAC & SD-FEC.
- Versal Prime — Baseline platform.
- Versal Premium — Premium platform with maximum adaptable engines and 112G transceivers and 600G IP.
- Versal HBM — Premium platform with support for HBM.
The first Versal devices, Prime and AI Core, will be available in the second half of 2019. Followed by Versal AI Edge, Prime and AI RF in 2020 with the Versal HBM offering being available in 2021.
At the core of the Versal, portfolios are the intelligent, scalar, and adaptable engines as well as the domain-specific interfaces.
But what exactly are they?
Scalar Engines — The scalar engines contains dual-core Arm Cortex-A72 application processors (ARMv8-A 64-bit instruction set), dual-core Arm Cortex R5, and a platform management controller that performs control over booting, power management and dynamic reconfiguration.
Adaptable Engines — New hardware fabric which has been re-architected to provide a create computational density, enable customizable memory hierarchy, and provide for faster, on the fly dynamic reconfiguration.
Intelligent Engines — There are two different type of intelligent engines available: DSP and AI. DSP engines provide high precision floating point with low latency performance intended for customized data paths. While the AI engine is a software programmable vector processor array with tightly coupled memory that provides high throughput low latency capabilities ideal for AI inference.
Domain Specific Interfaces — Advanced protocol engines and interfacing solutions. These domain specific interfaces include PCIe (Gen4x16) and CCIX, support for DDR4–3200, LPDDR4–4266 and high bandwidth memory. 100G multi-rate Ethernet, 600G Ethernet and Interlaken, along with providing 600G cryptographic engines for AES, IPSEC and MACSEC. Transceiver solutions offer 32G, 56G PAM4, and 112G PAM4. Finally, the RF series of devices will contain next generation GSPS RF-ADC / DAC with integrated up and down converters. These next-generation RF-ADC / DAC will be able to support a complete 800MHz 16x16 remote radio unit.
Communication and data transfer internally between the engines, and with the interfaces are provided by a network on chip. This offers multi-terabit/sec throughput with a guaranteed QoS.
Enabling solution creation which leverages the three heterogeneous processing engines and domain-specific interfacing is a new integrated software development environment.
Most interestingly, ACAP has been designed to work out of the box with no RTL flow.
The software development environment itself offers multiple entry points, allowing developers to work at the level of abstraction required for their solution. This includes working with frameworks (data scientists), C with optimized libraries (software developers), and of course, RTL (hardware designers).
In my view, this announcements is a true game-changer. It provides the developer with a solution that is:
- Adaptable — It has the ability to adapt to rapidly changing algorithms and requirements in areas which are experiencing not only rapid adoption and roll out but also still undergoing rapid evolution as to the best methods of implementation. This is critical for applications like AI.
- Software defined — It enables developers to work at a higher level of abstraction, with common frameworks and implement them within the appropriate Versal engine.
- Acceleration — The three different engines allow the system to be optimized to provided accelerated performance for a range of applications from AI to 5G and beyond.
I really look forward to getting my hands on one in due course, I hope, and see what I will be writing about over the next five years.
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