MicroZed Chronicles: Designing with Power Constraints

Several of the projects I am working on at the moment are required to work with power constrained supplies.

Adam Taylor
5 years ago

Several of the projects I am working on at the moment are required to work with power constrained supplies.

There are a number of reasons why the design is power constrained — from being expected to operate via a battery for a long period of time to operating in a environment where the thermal dissipation is tightly controlled.

So what should we consider when we are required to achieve tight power constraints?

  • Create a power budget — Right at the very start of the project, identify all of the voltages rails necessary for the solution along with the currents associated with each of those rails. Of course, one quick win here is to minimize the number of rails required and hence reduce the conversion losses. Once this budget has been completed and reviewed by all involved in the design we can start working on the more detailed implementation with everyone knowing what their budget is. This is also the point at which you may wish to reserve a portion of the budget as contingency. If you are reserving a contingency ensure that no one else is either at a higher or lower level in the development. Otherwise you end up with increasingly tight budgets caused by contingency on contingency. Of course, this budget should be kept current, being refreshed throughout the project as the design matures.
  • When it comes to device selection we should try to select the smallest device in the largest package available. A larger package provides a greater surface area enabling greater heat dissipation . If possible we should also select devices which are available in lower power and lower leakage options.
  • As we start to architect our FPGA / SoC solution, we will begin to firm up on the IP blocks used, new IP to be created, pin out, clocking and reset strategy, etc. This is the perfect time to also start calculating the it’s power requirements. To help us do this, Xilinx provide several XPE spreadsheets which can be downloaded here for different device families. Using this spreadsheet we can not only determine we are within the power budget, we can also consider a number of what if scenarios. In this spreadsheet we can also define a range of conditions from board stack up, to ambient temperature, heat sink solutions, and air flow.
  • Carefully consider the IO standard and configuration used. If single ended standards are deployed, select the lowest voltage, drive strength and slew rate that will be accepted by the receiver. If differential standards are used consider the use of reduced swing standards. For all standards carefully consider the termination scheme, prefer serial over parallel.
  • Once the design is completed and ready to be implemented, we need to ensure we have correctly configured Vivado to provide a power optimal implementation. Power optimization is performed in two implementation stages: optimization and power optimization. Optimization is focused on BRAM power optimization and does not require enabling by the user. Power optimization, however, is not run by default as it might impact performance — it is enabled as part of the implementation settings, to provide control over the power optimization we can define power constraints to limit actions to specific nets or clock domains.
  • Once we have implemented the design with the power optimizations configuration as desired, we need to open the implemented design and run the power report. To get an accurate power report, we need to ensure the confidence level for all parameters is high. We can set these parameters using the power report dialog. If necessary, we can also use this to pull in Switching Activity Interchange Format (SAIF) files which can be generated from simulation. We will examine in detail how to generate this file in a blog soon. The output from this report can be fed back into the XPE and used for further analysis.
  • One additional feature we should consider when using a Zynq, Zynq MPSoC or RFSoC is we can further optimize for power by powering down unused cores, etc. If we are using a operating system such as Linux, the OS will perform power management of the cores as it is running. But, if we are using the MPSoC/RFSoC we can also use the platform management unit to disable a power islands within the device which are not currently being used.

A few final notes, when we are undertaking the power estimation and analysis, we should try to use try to calculate the worse case power conditions. This means that we should use maximum process settings and set the device supplies to the maximum voltage supplied by the power solution. We should also ensure we perform the analyse at the maximum ambient temperature the system will be operating at. If we do not do this we may find a corner case during test, qualification or even worse in the field which causes issues.

Used together and with careful consideration, the above techniques and tools provide us with a good chance at achieving a design which meets our power budget.

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Adam Taylor
Adam Taylor is an expert in design and development of embedded systems and FPGA’s for several end applications (Space, Defense, Automotive)
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