The ability to add a high-level operating system to your SoC brings with it several advantages. It enables us to have several different applications running thanks to multi-tasking and it greatly eases implementing network and communications.
Of course, it is also used by a wide range of software developers, who are familiar with working with Linux, helping accelerate the application development.
In this blog and the next one, we are going to look at how we can build a MicroBlaze system which runs Linux.
The first thing we need to do is build the hardware design in Vivado which is what we will be looking at in this blog. To do this, we will be using the following IP that will create a simple system:
- MicroBlaze Processor
- Memory Interface Generator
- AXI Dual Timer
- AXI UART Lite
- AXI Ethernet Lite
- AXI Interrupt Controller
- AXI GPIO
- AXI QSPI
For this blog, I will be targeting the Artix 100T device.
The first step in the design process is to add in the MicroBlaze processor. We need to configure this to be able to run Linux as such from the drop-down menu I selected Linux with MMU for the configuration.
I then left the next three pages of options unchanged; however, on page 4 I did increase the size of the cache to 64KB.
The final adjustment was on page seven to enable the AXI Interfaces.
With the processor placed on the block diagram, the next stage was to implement the MIG and clocking.
The MIG is generated to support a 256 MB DDR3L.
With the processor and the MIG instantiated, the next thing to address is the clocking, for which I used a clock wizard.
The clock wizard generates the Clkin and Sysclk clocks for the MIG. These frequencies are 200 MHz and 166.6667 MHz, respectively.
The MicroBlaze and the reset of the AXI peripherals are clocked from the UI clock output from the MIG.
As I added in the rest of the AXI components identified above, the only other change I made was to the UART to set a baud rate of 115200.
With everything all included in the design, the final stage before verifying the design and building the image is to ensure the address map looks correct.
The completed design looks as below — I will put the TCL description on the GitHub.
A less complicated view of the same design showing only the AXI interconnects is also shown for clarity.
When I implemented this design in the target device, not surprisingly as I was targeting a larger device left lots of room to add in the remainder of my IP.
With that I built the project, generated the bit stream and exported it to SDK. Before I build the PetaLinux image, I want to ensure the base MicroBlaze design is working as expected.
To do this, I created two projects — the first the simple hello world project, the second a project to test the external DDR.
Creating the hello world program is very straight forward, and we have done it several times over the years.
When I ran this program on the MicroBlaze (running from the internal Block RAM), I received a hello world message as would be expected.
This gives me some confidence that I can connect to and work with the MicroBlaze; although, I still want to know the memory is good before I spend the time building the PetaLinux image.
To do this, I am going to create a new application which shares the same BSP as the hello world application. This time I am going to use the pre-defined memory test application.
Once the memory test has been generated, we need to ensure that we are running the program from the on-chip memory and not DDR as that is what we want to test.
As such, select the project in the project explorer, and then go to Xilinx->Generate Linker Script.
This will open the linker script generation dialog which allows us to define the area of memory the program runs from. In this case, it will be the Local BRAM.
Once this program has been created, we can build the ELF file and run it on the hardware using a debug session.
You will see above in the memory test that the application successfully ran and that we can be sure the DDR is correctly configured in the design.
We are now ready to build the PetaLinux image which I will leave until next time!
Part Two can be found here
See My FPGA / SoC Projects: Adam Taylor on Hackster.io
Get the Code: ATaylorCEngFIET (Adam Taylor)
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