LowRISC Highlights Ibex Core System-on-Chip Implementations, Nexys Video Artix-7 Support

New users can choose between a minimal implementation from Tobias Wölfel, or a fully-featured microcontroller design from the PULP Project.

Gareth Halfacree
9 months agoInternet of Things

Free and open source silicon specialist lowRISC's Pirmin Vogel has highlighted two ready-to-run implementations of its Ibex RISC-V soft-core processor, formerly known as Zero-riscy, including one which has just gained support for the Digilent Nexys Video Artix-7 FPGA development board.

Originally developed at ETH Zürich as the Zero-riscy core and contributed to the lowRISC project in December 2018, the Ibex core is designed as a compact, high-efficiency 32-bit RV32IMC microcontroller core with a range of configuration parameters allowing it to be tuned to particular application scenarios. "Our microcontroller-class RISC-V processor core Ibex for sure is a solid base with which to start your own project," writes Vogel, before admitting that "to actually get your own RISC-V system running, quite some more infrastructure might be needed besides the bare processor core."

The solution comes in two ready-to-run system-on-chip designs which implement the Ibex core. The first, bundled with the Ibex source code and contributed by community member Tobias Wölfel, is positioned as a minimal example designed to showcase integration of an Ibex core into a top-level design, including the connection of memories and the compilation and execution of a simple program, and runs on the Digilent Arty A7 FPGA development board.

The second is a somewhat larger-scale project: PULPissimo, a microcontroller-focused design which started life with the Zero-riscy core at its heart before reintegrating Ibex following its adoption by lowRISC. Featuring micro direct memory access (uDMA) for autonomous input/output subsystem management, a JTAG debugging module, support for hardware processing elements, and support in the PULP software development kit, the Ibex-based PULPissimo release now supports the Digilent Nexys Video Artix-7 FPGA development board.

"This board is equipped with a XC7A200T device — the largest Artix-7 FPGA supported by the free Vivado WebPACK Edition — and thus an attractive target for hobbyists," Vogel explains of the decision to port to the Video Artix-7. "Ibex utilizes a fairly small part of the overall resources (3500 LUTs, roughly 2.6% of the available resources). There is still plenty of space available for you to implement you own modules such as custom accelerators!"

The Ibex core and Arty A7 example are both available on the lowRISC GitHub repository; PULPissimo can be found on the PULP Platform repository. Vogel's full post, meanwhile, is available on the lowRISC blog.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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