Ken Shirriff Reverse Engineers the Xilinx XC2064, the World's First Field-Programmable Gate Array
With just 64 logic blocks, Xilinx's original XC2064 was the first implementation of Ross Freeman's patented FPGA technology.
Ken Shirriff has turned his noted die-analysis reverse engineering skills on a field-programmable gate array (FPGA) with a difference: It's the first-ever FPGA, Xilinx's XC2064.
"The FPGA was invented by Ross Freeman who co-founded Xilinx in 1984 and introduced the first FPGA, the XC2064." Shirriff explains of the part's importance. "This FPGA is much simpler than modern FPGAs — it contains just 64 logic blocks, compared to thousands or millions in modern FPGAs — but it led to the current multi-billion-dollar FPGA industry. Because of its importance, the XC2064 is in the Chip Hall of Fame."
"An FPGA is configured via the bitstream, a sequence of bits with a proprietary format. If you look at the bitstream for the XC2064, it's a puzzling mixture of patterns that repeat irregularly with sequences scattered through the bitstream. There's no clear connection between the function definitions in XACT and the data in the bitstream. However, studying the physical circuitry of the FPGA reveals the structure of the bitstream data and it can be understood."
For his analysis, Shirriff turned to some key sources. First was the original patent, filed by Freeman in 1984 and granted in 1989. While that describes the theory of operation, including a number of useful diagrams, it does not cover the actual physical implementation — for which Shirriff turned to his usual trick of analysing high-resolution photos of the silicon die within the chip, uncovered through the destructive process of "de-capping."
What follows is a deep-dive into the components which made the XC2064 possible, how they are arrayed, and how that relates to the bitstream by which it is configured. "Two concepts are the key to understanding the XC2064's bitstream," Shirriff concludes. "First, the FPGA is implemented from 64 tiles, repeated blocks that combine the logic block and routing. Although FPGAs are described as having logic blocks surrounded by routing, that is not how they are implemented."
"The second concept is that there are no abstractions in the bitstream; it is mapped directly onto the two-dimensional layout of the FPGA. Thus, the bitstream only makes sense if you consider the physical layout of the FPGA."
Shirriff's full analysis is available on his website, along with a link to a work-in-progress application which can take a bitstream file and generate the configurable logic block (CLB) information.