Jeremy King Sets His Sights on Recreating Intel's Venerable 4004 CPU — And a New Pipelined Version

Computer engineer and vintage computing enthusiast Jeremy King is working on recreating Intel's first microprocessor, the venerable 4004, in open source Verilog suitable for implementation on an FPGA or manufacture as a physical chip — and has set himself the challenge of following up with two "what-if" spin-off designs, dubbed the Pipelined 4004 and RISC-4.

"The Intel 4004, designed by Federico Faggin in 1971, was the world's first single-chip microprocessor. It contained 2,300 transistors and enabled the microcomputer revolution," King explains of the original chip that inspired the project. "This recreation honors Faggin's pioneering work by bringing his design into the modern era of open-source silicon."

The 4004 was one of the first successful commercializations of the at-the-time new concept of large-scale integration (LSI) in integrated circuits — turning a central processing unit from a collection of parts to a single physical chip, though the 4004 was originally designed as part of a chipset to drive a printing calculator. The success of the project would lead Intel to build the successive 4040 and the eight-bit 8008 and 8080 — the latter of which would directly inspire the company's breakthrough x86 architecture.

King is taking the project seriously: "I am traveling to Italy to visit Olivetti (where Faggin started his career), his hometown of Vicenza, and to study the history that led to this revolutionary chip," he explains, a trip that is running alongside the physical work of reverse engineering the processor to create a cycle-accurate recreation in Verilog, which can be used to create a 4004-compatible on an FPGA.

King's vision goes further, though: he plans to also produce physical chips, using multi-project wafer offerings that bring the cost of silicon manufacturing down to the low-five-figures. Beyond that, the engineer has plans for two "experimental cores" inspired by the 4004: Core B, a "Pipelined 4004" that uses a five-stage pipeline and four-bit parallel execution to deliver significantly improved performance without losing binary compatibility with the original 4004; and Core C, the "RISC-V," a clean-slate four-bit architecture designed with efficiency in mind.

More information on the project is available on King's GitHub repository, where everything is being published under the permissive Apache 2.0 license.

Main article image courtesy of Thomas Nguyen, CC-BY-SA 4.0 International.