Jane Street Invites FPGA Developers to Try Their Hand at Solving Advent of Code Puzzles
Advent of FPGA takes the annual programming challenge series and applies it to hardware, with a dev kit up for grabs for the best entry.
Jane Street has launched a competition for FPGA developers, using the puzzles set during this year's Advent of Code to promote solutions based on synthesizable hardware — and entrants can win prizes up to and including an AMD Zynq UltraScale+ Kria KV260 FPGA development kit for their entries.
"Advent of Code has long been a favorite December ritual at Jane Street, with many participating in the month-long puzzle challenge that encourages thoughtful engineering and out-of-the-box thinking — very much our kind of fun," Jane Street's Benjamin Devlin explains. "Last year, Anish, a hardware engineer at Jane Street, wrote about tackling the entire series in Hardcaml, our OCaml-based hardware DSL, turning these puzzles into synthesizable FPGA circuits. If you missed it, his post, Advent of Hardcaml, walks you through how implementing such algorithms in hardware became a unique exercise in architectural design and resource optimization."
Now, the company is looking to encourage others to do the same with the 2025 Advent of FPGA challenge. The idea: taking the programming puzzles set each year by Eric Wastl, who founded the Advent of Code challenge series back in 2015, and solving them in hardware rather than software.
"When the final AoC 2025 puzzle drops, pick any puzzles you like (at least one and up to as many as you want) to build synthesizable RTL with realistic I/O [Input/Output]," Devlin and Anish Singhani explain. "Bonus points if you do it in Hardcaml. We're excited to see the clever designs created across the academic and open‑source communities, and we’d also love to get more people trying Hardcaml!"
More information on the competition, entries for which close on January 16, 2026, is available on the Jane Street blog.