Hackster's FPGAdventures: Building Logic Using Libero SoC on the Microchip PolarFire SoC Icicle Kit

Using the clever SmartDesign it's possible to build FPGA gateware block-by-block without touching the underlying code — if you persevere.

Gareth Halfacree
23 days agoFPGAs / HW101

So far in our FPGAdventures we've been playing with pretty much everything bar the FPGA itself, looking at how the general-purpose processing portion of the PolarFire SoC at the heart of Microchip's Icicle Kit can be used to run everything from a fully-functional Linux distribution to bare-metal code — even both at the same time, courtesy of the platform's clever asymmetric multiprocessing (AMP) capabilities.

This time around, we're diving into the real meat of the kit: using Libero SoC, Microchip's integrated development environment (IDE) and toolchain for its FPGA products, to create a basic logic circuit, synthesize it, and deploy it to the board.

Hungry, hungry programs

The first thing to understand about Libero SoC, once you've gone through the hoops required to register for a free license and deploy the archaic license validation server on your workstation, is that Microchip's system requirements are far from a recommendation, but rather an absolute requirement: when the company tells you that you'll need 16GB of RAM, you need to make sure you've got at least 16GB of RAM available. Running the software with less is possible, which can mislead you into thinking everything's going fine — but you'll find your projects failing without error during the synthesis stage. The place-and-route tool exhausts system RAM and falls foul of the out-of-memory killer, even for the most simplistic of designs, exiting in a way that fails the process but without a corresponding error to point you towards the problem.

Once you've got a suitably-meaty workstation to hand, you need to start learning the ins and outs of what is a very busy user interface. The good news for a maker coming in to all this from the cold is that Microchip has a step-by-step guide, which walks you through the process — from starting your first project to synthesizing the bitstream and flashing it onto the FPGA. It's very much an on-rails tutorial, but enough to get you started and learning the basics of the somewhat-cluttered Libero SoC interface. Unfortunately, it's not actually directly applicable to the PolarFire SoC Icicle Kit; instead, it was written for the company's earlier PolarFire Splash Kit.

For the majority of the process, that doesn't matter. Starting a new project is the same for any of Microchip's development kits or bare FPGA products, though you'll need to figure out which of the numerous variants of PolarFire SoC you're working with to set the environment up correctly. It's really only when you've reached the nitty-gritty part of the process and start designing something you'll run into an actual hurdle, though: The pin numbers and functions of the PolarFire SoC do not match the earlier PolarFire, and as a result the tutorial's instructions for the PolarFire Splash Kit can't be applied to the PolarFire SoC Icicle Kit directly.

Picking a pin

There's no real quick fix for this bar the obvious: swapping out the suggested pin numbers for ones available — and of practical use — on the PolarFire SoC Icicle Kit. To do that you need to pull up the PolarFire SoC's schematics and drill down into the pin numbering to figure out what inputs and outputs you could apply to your design to have it actually do anything useful; there's no handy default mapping in Libero SoC, which would allow you to, say, select "LED1" from a drop-down list. This, then, should be step one of any given project — and you may find it useful to make a little cheat-sheet of common pins to have close to hand while working with the Icicle Kit.

There is an alternative approach, though not one discussed in the company's tutorials: the PolarFire SoC Icicle Kit Reference Design, published by Microchip to GitHub under an unspecified open-source license. This provides a script that can be loaded into Libero SoC to generate gateware with, the company explains, "the same or extended functionality" as that already loaded onto the FPGA from the factory — handy if, having progressed considerably further along the learning curve than the tutorials will guide you, you want to extend or enhance the stock functionality rather than replace it outright.

Loading the script into Libero SoC deviates from the step-by-step tutorial, but it is possible to combine the two approaches into one. "It's very useful as a jump-start," Microchip's Leonardo DiCarlo explains of the reference project. "You don't even need to generate the project, you can simply use for reference the same constraints used there. In the [file] ICICLE.pdc you find the usual things used for tests like switch buttons, LEDs, etc. You can directly import that file. You just have to be sure that the name of the output port you used matches the one used there, otherwise you can just modify the name."

SmartDesign for smart designs

As you might expect from an enterprise-grade tool for FPGA development work, Libero SoC isn't the most welcoming software to newcomers — makers included. Microchip's guides will get you so far, but you're definitely going to have to spend a long time playing with it before you feel confident — particularly if you're coming to FPGAs from a more immediately-accessible platform like microcontrollers.

It's worth the investment — and Microchip's SmartDesign is key to getting you on your feet as quickly as possible. Traditionally, gateware for FPGAs is written by hand using a hardware description language (HDL) — a text-based approach analogous to writing MicroPython for a Raspberry Pi RP2040 or C/C++ for an Arduino. SmartDesign is something closer to Scratch, but for FPGAs: hardware designs can be sketched out on-screen as schematics, and are automatically turned into HDL code — and, from there, gateware — by Libero SoC.

Better still, Microchip provides a healthy library of components that can be loaded into Libero SoC and used as the building blocks for your gateware design — everything from basic Boolean logic gates to memories and input/output devices. The library can be freely searched, though parts are often given names like "DFN1C0," which are perhaps a little oblique for the newcomer, and a chosen object simply dragged onto the SmartDesign Canvas — where it turns into a schematic symbol.

Yes, AND

To test the functionality out, we followed the guidance in Microchip's tutorial and picked possibly the simplest component around: a Boolean AND gate, which sends its singular output high only when both of its inputs are also high. Adding to the the design is a simple case of drag-and-drop, though wiring its inputs and outputs takes a little longer.

For our simple AND gate design, we need two inputs — push-button switches, to make things as easy as possible when it comes time to test in hardware — and a single output. Peering through either the schematic or the sample project files reveals that pin V14 connects to LED1, giving us our output; V19 and U18 connect to a push-button switch each, providing the two inputs we'll need to interact with our basic FPGA design. If we wanted to wire in external buttons, other pins connect to the Raspberry Pi-style general-purpose input/output (GPIO) header or the mikroBUS socket — but for our purposes the on-board push-button switches will work fine.

Once the part's virtual legs are wired up, which does require a few less-obvious steps including "promoting" its connections to "top level," creating the HDL is a one-click process. At this point, the memory requirements for Libero SoC haven't been a problem — but the next step of the process, synthesis, is where the software begins to eat up RAM. Double-clicking the Synthesize option in Design Flow begins the process of turning your creation into gateware loadable onto the FPGA, calling an external tool called Synplify Pro — a license for which is included in the free Libero SoC license available to all PolarFire SoC Icicle Kit users. It's this which handles the "compilation" of the HDL, including place-and-route — the FPGA equivalent of putting component footprints onto a PCB and linking them with circuit traces.

For a simple design like the AND gate, it's a fairly quick process — but as the design complexity increases so to does the time, and memory, required for synthesis. Make your design too complex and you'll run out of resources on the FPGA — in exactly the same way you can run out of memory or program storage on a microcontroller — and have to scale it back, or pick up a higher-specification chip in the PolarFire SoC family.

Skipping a step

Once synthesis is completed, it's possible to deploy the gateware onto the FPGA — though not recommended. Instead, FPGA designs should first be run through simulation — that is where Microchip's documentation takes a quick step back. The company's PolarFire Splash Kit tutorial, which we've been following until now bar the changes required for PolarFire SoC compatibility, completely skips this step — and it's hard to blame the company for that, as it's an extremely complex subject. Everything you need is there in Libero SoC, but while finding it is pretty straightforward actually being able to use it is a lot of learning away.

Skipping simulation provides a quick route to the payoff of being able to press buttons on the Icicle Kit and have an LED go on and off as a result — proving that you did, in fact, create a functional AND gate, which is tied into the pins of your choosing and, from the pins, the push-button switches and LEDs of the Icicle Kit — but won't help you when it comes time to design more complex projects.

Making for makers

And it's here that Microchip's hopes to see the PolarFire SoC Icicle Kit broadly adopted in the maker community, rather than just industry and academia, could fall down. Its beginner-friendly documentation is written for an older development board, not the shiny new PolarFire SoC Icicle Kit, and abandons the reader before what is arguably both the most complex and most vital part of the design flow; without new material better-suited to the company's new target audience, many makers are likely to abandon the platform for something more approachable before ever getting anything more complex than an adder built.

If that's so, it's a shame: the power and flexibility of the PolarFire SoC is impressive, as its its ability to combine FPGA and application-class general-purpose processing on a single device. There's so much potential for interesting creations, and if Microchip can find a way to break down the barriers there's little limit to what the maker community could do with both the Icicle Kit and the PolarFire SoC chips that drive it.

Join us next time when we'll be looking at some of the things the community has already been doing with the PolarFire SoC and talk with Microchip about its plans for the future of the platform.

More information on the PolarFire SoC Icicle Kit is available on the Microchip website and can be found on Avnet's product page as well.

Read the whole series:

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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