Fraunhofer IPMS, CAST Reveal 32-Bit RISC-V Processor with Edge AI, TinyML Enhancements

Fraunhofer IPMS and CAST have jointly announced an embedded processor designed for artificial intelligence at the edge, built around the free and open source RISC-V architecture — an upgraded version of CAST's earlier EMSA5-FS processor.

Launched earlier this year, the CAST EMSA5-FS is a 32-bit single-issue in-order RISC-V processor designed for energy efficiency in embedded and microcontroller scenarios. Already shipping, it's well-suited for a variety of tasks — but Fraunhofer IPMS found that it could be easily improved for tinyML and edge AI work with a couple of key tweaks.

The first: Porting the TensorFlow Lite framework to the chip, allowing easy access to the wealth of compatible models already available and ease of developing more. The second: Adding the Zve extensions, recently-ratified optional instructions which can be added to the core RISC-V instruction set architecture to offer high-performance vector processing — boosting the performance of AI workloads considerably.

“These additions to the EMSA5-FS Processor core now enable the execution of vector instructions that allow parallel processing of datasets and can consequently improve performance as well as energy efficiency,” claims Andreas Weder, PhD, group manager for module integration at Fraunhofer IPMS, of his company's work. “Our users can now reliably implement Edge AI applications such as gesture recognition or vibration analysis."

While the upgraded processor has been announced, however, it's not yet ready for use: The companies have confirmed that the TensorFlow Lite port will be publicly available via CAST in the first half of 2022, and that EMSA5-FS cores with the Zve extensions will follow shortly after.

Information on the EMSA5-FS itself, meanwhile, is available on the CAST website.