RISC-V Ratification Process Results in 15 New Specifications for Machine Learning, the IoT, and More

RISC-V International has announced the ratification of 15 new specifications for extensions to the free and open source RISC-V instruction set architecture, including extensions for vector, scalar cryptographic, and hypervisor virtualization workloads — giving the ISA new impetus in fields including machine learning and the Internet of Things (IoT).

"In 2021, RISC-V International made huge leaps in our technical progress as we ratified 15 specifications that are critical for the future of computing," says Krste Asanović, chair of the RISC-V International board of directors, of his organization's work. "The development of these specifications really showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements."

Representing 40 individual extensions, which offer optional new instructions designed to accelerate or otherwise improve the efficiency of selected workloads on RISC-V cores, the 15 newly-ratified standards include three of particular interest: Vector extensions, designed to boost performance for tasks including machine learning workloads; scalar cryptography extensions for boosted security functionality in resource-constrained fields like the IoT; and a hypervisor specification for hosting virtual machines in the cloud and beyond.

"The new RISC-V Vector specification will change the way people think about vector designs," claims Dave Ditzel, founder and executive chair of RISC-V International member Esperanto Technologies. "With just over 100 instructions, the extension offers a simple and elegant approach to efficiently process the latest machine learning algorithms."

"The RISC-V Scalar Cryptography extensions allow for implementing standard cryptographic hash and block cipher algorithms that are an order of magnitude faster than using standard instructions in some cases. With RISC-V’s transparent and open approach, anyone can efficiently implement critical cryptographic algorithms in any class of CPU," adds Ben Marshall, cryptographic hardware engineer at PQShield and member of the RISC-V Technical Steering Committee responsible for the extensions. "In addition to the performance benefits, these new extensions are very cheap to implement so companies can integrate popular cryptography algorithms in even the smallest connected devices."

As with all the standards from RISC-V International, the newly-ratified extensions are provided under permissive licensing terms for anyone to use while building RISC-V devices. The latest specifications are available on the RISC-V website, while the wiki includes a list of the extensions most recently ratified by the organization.