Espressif's Teo Swee Ann Confirms a Shift to RISC-V by Default, "Unless We Have Some Special Needs"

Espressif chief executive and president Teo Swee Ann has confirmed that the company will be concentrating exclusively on parts built around the free and open source RISC-V instruction set architecture, marking the end of an era for its popular Tensilica-based range.

Espressif is best known as the company behind the ESP8266 and ESP32 families of embedded systems-on-chip (SoCs). Found at the heart of everything from hobbyist development boards to commercial products, the majority of the chips are built around microcontroller cores from Tensilica - the Tensilica Diamond in the ESP8266 and the Tensilica Xtensa in the ESP32.

Recently, however, the company has begun launching ESP32 parts that feature cores designed on the free and open source RISC-V instruction set architecture instead. Initially, these RISC-V cores appeared as coprocessors alongside one or more primary Tensilica cores; lately, however, the company has announced an increasing number of parts which are exclusively RISC-V — including its ESP32-C3 and most recently-announced footprint-reduced ESP32-C2.

Responding to a query on LinkedIn as to whether reports that the company was moving to RISC-V exclusivity, Espressif chief executive and president Teo Swee Ann made it clear: RISC-V is the way forward for the company. "Yes, it is true," Teo writes of the company's move to RISC-V. "Unless we have some special needs for something else, that I don't see now."

Those interested in learning more about the ESP32-C2, which is now sampling, can visit Teo's blog post on the topic.