Espressif's ESP32-C3 Leaks as a Drop-In Pin-Compatible RISC-V Replacement for the Popular ESP8266

After the introduction of an ultra-low-power RISC-V core in the ESP32-S2, Espressif is looking to launch its first RISC-V-only part.

Gareth Halfacree
2 months ago β€’ Internet of Things

UPDATE (11/30/2020): Espressif has confirmed the leak, officially announcing the ESP32-C3 as its first fully-RISC-V-based microcontroller product.

"ESP32-C3 attempts to address the most common needs for connected devices," the company explains. "Security is of prime importance. Even the lowest-cost connectivity solution needs to provide an appropriate level of security for common security threats. Bluetooth Low Energy availability is useful for improving user experience and field diagnostics. While cost is a very important parameter, the availability of sufficient memory for common use-cases is equally important."

The company's official announcement includes confirmation that the part is based on a 32-bit single-core RISC-V microcontroller running at up to 160MHz with 400kB of static RAM (SRAM), 2.4GHz Wi-Fi and Bleutooth Low Energy 5.0 support, and 22 programmable general-purpose input/output pins.

Espressif's announcement can be found on the company website, along with a link to the part's datasheet.

Original article continues below.

Details of Espressif's next system-on-chip design, the ESP32-C3, have leaked ahead of schedule β€” and reveal a switch to the free and open source RISC-V instruction set architecture for the main processor, a first for the company.

Espressif's ESP family of microcontrollers has long been popular with makers and tinkerers thanks to its flexibility and low cost. The ESP8266 has been the basis for a number of builds requiring Wi-Fi connectivity, while the ESP32 offers improved performance. The ESP32-S2, meanwhile, boosted specifications still further β€” and broke ground by adding an ultra-low-power coprocessor based on the free and open source RISC-V instruction set architecture.

Now, it looks like Espressif is making the jump from Arm to RISC-V: Details have leaked of the ESP32-C3, the company's upcoming ESP32 entry, with claims it will be the first to use a RISC-V core as its primary processor β€” ditching Arm entirely.

According to details leaked via Twitter, first spotted by CNX Software, the ESP32-C3 is designed to replace the ESP8266 as a drop-in replacement. A preliminary block diagram confirms a 32-bit RISC-V primary processor running at up to 160MHz, 2.4GHz Wi-Fi 802.11b/g/n and Bluetooth 5.0, Bluetooth Low Energy (BLE), and Bluetooth Mesh connectivity, a real-time clock, cryptographic acceleration, and a range of on-board devices including GPIO, I2C, I2S, SPI, PWM, UART, GDMA, USB, TWAI, ADC, RMT, timers, and a temperature sensor.

Leaker Johnny Wu also claimed the parts will include 400kB of static RAM (SRAM) and 384kB ROM β€” figures backed up by a leaked datasheet marked "pre-release version 0.3" and bearing a 2020 copyright date. Software development, meanwhile, would take place in an updated framework compatible with existing ESP8266 applications.

Espressif has yet to confirm the leak, with more details available in the ESP32.com forum.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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