Espressif's 240MHz ESP32-S2 SoCs, Modules, and Boards Enter Mass Production with RISC-V Coprocessor

The ESP32-S2's main 240MHz Xtensa LX7 CPU is joined by an ultra-low-power RISC-V coprocessor built into the RTC block.

Gareth Halfacree
3 months agoHardware 101

Espressif has announced that its next-generation ESP32-S2 systems-on-chip (SoCs), modules, and related development boards are now in mass production — offering up to 240MHz operation and 320kB of static RAM (SRAM), along with a range of security enhancements — and, for the first time, a RISC-V coprocessor.

The latest in the ESP32-S family, which launched last year as an upgrade to the ESP32 with a focus on security and cryptography functionality, the ESP32-S2 is based on a 240MHz Xtensa 32-bit LX7 single-core processor and includes 320kB of on-board static RAM (SRAM) alongside 128kB of flash ROM. Interestingly, the part also includes an ultra-low-power coprocessor based on the free and open source RISC-V instruction set architecture.

The ESP32-S2 includes 802.11b/g/n Wi-Fi connectivity on the 2.4GHz band, as with its predecessors, but also adds time-of-flight (TOF) calculation for ranging calculations. The SoC also includes RSA secure boot functionality, AES-XTS encryption of the flash memory and pseudo-static RAM (PSRAM) memories, cryptographic acceleration for Transport Layer Security (TLS) connections, and claimed defences against fault injection attacks and key leakage vulnerabilities.

As well as the bare ESP32-S2 SoC, Espressif has confirmed mass production for two module variants — ESP32-S2-WROVER and -WROOM — and a pair of development boards dubbed the ESP32-S2-Saola-1 and the ESP32-S2-Kaluga-1. The latter of these is designed for human-machine interface (HMI) application development, offering an on-board touchscreen display, camera connectivity, audio playback, and 43 general-purpose input/output (GPIO) pins.

More information is available on the Espressif website.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire:
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