Etching PCBs? Sam Zeloof Steps It Up a Notch, and Down a Few Orders of Magnitude, with His Own ICs!

While perhaps less commonplace these days, it use to be a rite of passage in the electronic engineering field to have etched your own PCB at least once.

With the advent of PCB pool services like OSH Park, the telltale signs of a homebrew PCB artist are certainly lesser seen. The brown stains of Cupric Chloride solution over clothing — and often fingers — would look strange and unexplained to many a younger maker.

It's kind of sad to think we are approaching the generation where the bubbling etch tank might be left laid aside to gather dust, and the UV lamps of the photoresist exposure box left long unlit.

Despite that, there will likely always be a hardcore contingent of people who are happy to stain up the kitchen, cranking out custom PCBs for some time to come yet!

I say hardcore. Perhaps that was appropriate classification — until now.

There's a new bar placement for "hardcore" in the homebrew hardware world, and Sam Zeloof has cleared it in style!

IC, μC — Sam Zeloof is opening the door to custom chips for people like you and me!

While there are actually full chip fabrication services that can be engaged by the likes of you or I, Zeloof has shown full autonomy from those by bringing the fabrication process home — into his actual home!

That's right, this is a one-man show — Zeloof is performing the full stack of substrate doping, photolithographic etching and mask placement and removal himself!

Rev 2...

If the packaged silicon shown above revives some distant memory, you may have caught the previous work of Zeloof, when he released news of his success with the Z1 chip — wayyy back in 2018!

Where as the Z1 was a suitably impressive feat in its own right — the first home made lithographically fabricated IC is no small achievement! — Zeloof felt that in the time passed since 2018, his skill and knowledge had improved enough to warrant a fresh challenge, with a new chip design that would rival the likes of Intel. Intel, way back in 1975, that is...

The Z1 was a six-transistor device, etched in a four-layer PMOS process, to form an analog amplifier.

With his recent work, Zeloof is now presenting us with the Z2 device, which is a huge increase in device density when compared to the modest, 6-transisor design of the Z1 — managing to pack 1200(!) individual transistors into roughly the same area of silicon that the Z1 occupied.

Although this is a test pattern and not a full interconnected IC design, these arrays of 100 individual transistors represent a mind-blowing increase in density — with a decreased feature size that allows many, many more gates to be placed into one of these homebrew ICs, so much so that Zeloof almost seems set to put Moore's law to shame!

Moore's law predicts more!

Who's law? Gordon Moore, the co-founder of Fairchild Semiconductor and co-founder / former CEO of Intel itself, famously predicted the number of transistors able to be packed into a chip would double approximately every two years.

While this is commonly interpreted as "computing power will double every two years", we are fast approaching physical limits that cause this law to breakdown as fast as an overvolted PMOS gate!

The laws of physics come up hard when you are poking around with polysilicon features fast approaching units of measure such as the Angstrom...

Though Zeloof isn't quite down on that feature scale just yet — the flip side is that he is able to leapfrog his advances in technology — far outpacing the rate of progression compared to the likes of Intel. Again, Intel back in 1975, that is...

Well if we look at the data, and compare the progress Zeloof is making to that of industry, we can clearly see that he's going to be giving Intel some trouble in about five years!

Of course, Zeloof will hit the same physical barriers in time, but that's an incredible thought in its own right — a homebrew polysilicon lithographic fab process that is fast catching up with the industry, even if some years in lieu.

Testing, testing, Z1, Z2... Z1, Z2...

It is of no surprise to see that Zeloof is focused on perfecting his polysilicon process. With the Z2 chip mask comprising 12, repeated test patterns, each of which composes an array of 100 N-Channel Field Effect Transistors (N-FETs) in a 10 x 10 grid, this mask pattern results in a staggering 1,200 individual transistor devices, on a chip measuring some few square millimetres!

With a (very) zoomed in view, Zeloof shows us the raw FET structure itself, with the

Zeloof has even characterised the properties of the polysilicon NFETs, as can be seen below — the results look very good — incredible for something produced outside of a clean room!

An individual array of 100 FETs occupies some 2.4mm^2 — about one quarter of the footprint of the previous chip design, the Z1.

Keep it clean!

This is mind-blowing stuff to come out of a garage lab.

Normally, devices like this are produced in high grade "clean rooms" - UV free fabrication lines with an insane amount of air filtration required — necessary to avoid errant particulate from contaminating the silicon, or obscuring the photolithography processes.

In quite the contrast, Zeloof shows us that you don't need a multi-million dollar facility to fabricate FETs! How many of our hackerspaces and workshops boast this sort of glovebox setup? This is a man who takes his craft seriously!

Scratching the surface

We have barely touched on the immense amount of information that Zeloof has chosen to kindly share with us. His personal website is a goldmine of technical knowledge, test reports and many more fascinating figures and musings on all things relating to the fabrication of homebrew integrated circuits!

If any of this has caught your interest, be sure to check out the write-up here, and additionally, be sure to give Zeloof a follow over on Twitter — @szeloof!