Cologne Chip's GateMate FPGA Offers a Flexible "Cologne Programmable Element" Architecture
Designed for flexibility and scalability, the GateMate FPGAs come with a partially-open toolchain — which could fully open up this year.
German electronics firm Cologne Chip has launched a new field-programmable gate array (FPGA), the GateMate CCGM1A1, which boasts a novel architecture capable of turning 20,480 Cologne Programmable Elements (CPEs) into either 20,480 eight-input LUT trees or 40,960 four-input LUT trees with 40,960 flip-flops or latches.
"The GateMate FPGA family of Cologne Chip AG addresses all application requirements of small to medium size FPGAs," the company claims. "Logic capacity, power consumption, package size, and PCB compatibility are best in class. GateMate FPGAs combine these features with lowest cost in industry making the devices well suited from University projects to high volume applications. Because of the outstanding circuit size/cost ratio, new applications now can use the benefits of FPGAs."
The driving force behind the new chips, which were brought to our attention by CNX Software, is the Cologne Programmable Element (CPE) architecture. In the launch version, the CCGM1A1 built on GlobalFoundries 28nm Super Low Power (SLP) process node, there are 20,480 CPEs — each of which can be treated as a single logic element with an eight-input lookup table (LUT) tree or two four-input LUT trees and two flip-flops or latches.
Along with this, the chip offers 1,280kb of block RAM configurable as 64 20kb blocks or 32 40kb blocks, a quad-SPI (QSPI) bus running at up to 100MHz, four phase-locked loops (PLLs), one serial-deserializer (SerDes) with 5Gb/s bandwidth, and 162 single-ended general-purpose input/output (GPIO) signals — configurable as 81 differential inputs if preferred. There are three "performance modes" ranging from lowest-power to highest performance and running the chip from 0.9V to 1.1V supply power, plus support for 1.2V to 2.5V GPIO signalling logic.
What makes the chip even more interesting is its use of free and open source software. Each GateMate is designed to use the Yosys framework for synthesis, though the toolchain isn't fully open: the place-and-route (PNR) step of development requires Cologne Chip's proprietary software, which is — at least — made available to users at no cost. The company has also telegraphed support for the open source nextpnr place and route software some time this year.
For those looking to get started with the chip, which is the first in a planned family of parts scaling up to the CCGM1A25 with 512,000 CPEs and 32,000kb of block RAM, the company has also announced a reference design evaluation board which includes USB connectivity, PMOD expansion, 64Mb of HyperRAM running at 166MHz, and 64Mb of QSPI flash. Alternatively, for the patient, open hardware specialist Olimex has announced plans to design a — likely more affordable — open source GateMate board of its own.
More information on the GateMate FPGA family is available on the Cologne Chip website.