Mastering Bare-Metal PWM on STM32F411 (Black Pill

Published June 23, 2026 © GPL3+

STM32 PWM in bare metal

By directly manipulating the registers, to generate pwm. No library, no HAL functions.

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STMicroelectronics STM32 Nucleo-64 Board

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Premium Female/Female Jumper Wires, 40 x 3" (75mm)

Story

Mastering Bare-Metal PWM on STM32F411 (Black Pill)

Introduction: Generating a Pulse Width Modulation (PWM) signal is one of the most fundamental requirements in embedded systems—whether you are driving servos, dimming LEDs, or controlling motor drivers. While high-level abstraction layers (like HAL or Arduino) can get a PWM signal up in a single line of code, they obscure the underlying silicon logic.

In this project, we are throwing away the libraries and configuring a general-purpose timer on the STM32F411CEU6 "Black Pill" from scratch using pure C and bare-metal register manipulation (CMSIS). We will configure TIM3 to drive two independent hardware PWM outputs on PB4 and PB5 simultaneously, completely bypassing the CPU once initialized.

How It Works: The Silicon Layer A hardware timer is essentially an autonomous high-speed digital counter. It uses the MCU's internal clock source (in this case, the default 16 MHz internal High-Speed oscillator, or HSI) and runs silently in the background.

The architecture relies on three primary 16-bit registers working in tandem:

Prescaler (PSC): Divides the incoming 16 MHz clock down to a manageable frequency. For a 1 MHz timer tick, we divide by 16 (PSC = 15).

Prescaler (PSC): Divides the incoming 16 MHz clock down to a manageable frequency. For a 1 MHz timer tick, we divide by 16 (PSC = 15).

Auto-Reload Register (ARR): The ceiling value. The counter (CNT) ticks up until it matches ARR, then instantly resets to 0. This governs the PWM Frequency.

Auto-Reload Register (ARR): The ceiling value. The counter (CNT) ticks up until it matches ARR, then instantly resets to 0. This governs the PWM Frequency.

Capture/Compare Register (CCR): The threshold value. A hardware comparator checks if CNT is less than CCR. This governs the PWM Duty Cycle.

Capture/Compare Register (CCR): The threshold value. A hardware comparator checks if CNT is less than CCR. This governs the PWM Duty Cycle.

The Mechanism (PWM Mode 1):

While CNT is less than CCR: The physical pin is pulled HIGH.

While CNT is less than CCR: The physical pin is pulled HIGH.

The moment CNT is greater than or equal to CCR: The pin drops LOW.

The moment CNT is greater than or equal to CCR: The pin drops LOW.

When CNT reaches ARR: The counter resets to 0, and the pin pulls HIGH again.

When CNT reaches ARR: The counter resets to 0, and the pin pulls HIGH again.

Step-by-Step Configuration Flow: Configuring bare-metal peripherals requires a strict order of operations across three layers: RCC (Clocks), GPIO (Routing), and the Timer Peripherals.

Layer 1: Powering the Blocks (RCC) By default, peripherals are clock-gated off to conserve power. A peripheral without a clock is completely unresponsive—writing to its registers does absolutely nothing. We must enable the clock for GPIOB on the AHB1 bus and TIM3 on the APB1 bus.

Layer 2: Routing Pins via Alternate Functions For a pin to carry a hardware-generated PWM signal, it must be detached from the standard CPU input/output register and handed over to the timer mux.

Set the pin mode to Alternate Function (0b10) in MODER.

Set the pin mode to Alternate Function (0b10) in MODER.

Map the pin to AF2 in the Alternate Function Low Register (AFRL), which explicitly wires PB4 to TIM3_CH1 and PB5 to TIM3_CH2 in silicon.

Map the pin to AF2 in the Alternate Function Low Register (AFRL), which explicitly wires PB4 to TIM3_CH1 and PB5 to TIM3_CH2 in silicon.

Layer 3: Timer Setup & Preload Buffers We calculate our registers using the standard formulas:

Frequency = input_clock / ((PSC + 1) * (ARR + 1))

Frequency = input_clock / ((PSC + 1) * (ARR + 1))

CCR = duty_fraction * (ARR + 1)

CCR = duty_fraction * (ARR + 1)

Crucially, we enable the Output Compare Preload bit (OCxPE). This acts as a vital safety buffer: when you update a duty cycle in your application loop, the hardware intercepts the write and waits until the current counting cycle completes before applying it, completely eliminating mid-cycle waveform glitches.

Common Gotchas & Troubleshooting:

No output on the pins? Ensure you enabled RCC->AHB1ENR and RCC->APB1ENR before touching any peripheral registers.

No output on the pins? Ensure you enabled RCC->AHB1ENR and RCC->APB1ENR before touching any peripheral registers.

Using TIM1 instead of TIM3? Advanced timers like TIM1 require you to explicitly set the Main Output Enable (MOE) bit in the TIM1_BDTR register, or the pins will stay completely dead.

Using TIM1 instead of TIM3? Advanced timers like TIM1 require you to explicitly set the Main Output Enable (MOE) bit in the TIM1_BDTR register, or the pins will stay completely dead.

Overwriting channels? When configuring channel properties in CCMR1, always use read-modify-write bitwise operations (|=). A raw assignment (=) to configure Channel 2 will silently wipe out your settings for Channel 1.

Overwriting channels? When configuring channel properties in CCMR1, always use read-modify-write bitwise operations (|=). A raw assignment (=) to configure Channel 2 will silently wipe out your settings for Channel 1.

Code

Code

#include "stm32f411xe.h"

void SystemInit(void) {}
void _init(void)      {}

/*
 * PWM on PB4 (TIM3_CH1) and PB5 (TIM3_CH2)
 *
 * Source: DS10314 Rev 8, Table 9, page 48
 *   PB4 → AF2 → TIM3_CH1
 *   PB5 → AF2 → TIM3_CH2
 *
 * Clock: 16 MHz HSI (default, no PLL)
 * PSC = 15  → timer_clock = 16 MHz / 16 = 1 MHz
 * ARR = 999 → PWM freq    = 1 MHz / 1000 = 1 kHz
 *
 * CCR1 = 250 → PB4 duty = 250/1000 = 25%
 * CCR2 = 750 → PB5 duty = 750/1000 = 75%
 */

int main(void)
{
    /* ---- Step 1: Enable GPIO Port B clock -------------------------
     * RM0383 Section 6.3.10 — RCC_AHB1ENR, bit 1 = GPIOBEN
     * Without this, all GPIOB register writes are silently ignored. */
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;

    /* ---- Step 2: Enable TIM3 clock --------------------------------
     * RM0383 Section 6.3.12 — RCC_APB1ENR, bit 1 = TIM3EN
     * TIM3 is on the APB1 bus on the STM32F411. */
    RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

    /* ---- Steps 3 & 4: Configure PB4 and PB5 for Alternate Function
     * RM0383 Section 8.4.1 — GPIOx_MODER, 2 bits per pin
     *   PB4 → bits [9:8]  = 0b10 (AF mode)
     *   PB5 → bits [11:10] = 0b10 (AF mode)
     *
     * RM0383 Section 8.4.9 — GPIOx_AFRL, 4 bits per pin (pins 0-7)
     *   PB4 → bits [19:16] = 2 (AF2 = TIM3_CH1)
     *   PB5 → bits [23:20] = 2 (AF2 = TIM3_CH2)
     * Source: DS10314 Rev 8, Table 9, page 48               */

    /* Set PB4 and PB5 to Alternate Function mode */
    GPIOB->MODER &= ~( GPIO_MODER_MODER4 | GPIO_MODER_MODER5 );
    GPIOB->MODER |=  ( GPIO_MODER_MODER4_1 | GPIO_MODER_MODER5_1 );

    /* Select AF2 for PB4 and PB5 (both in AFRL — pins 0 to 7) */
    GPIOB->AFR[0] &= ~( GPIO_AFRL_AFSEL4 | GPIO_AFRL_AFSEL5 );
    GPIOB->AFR[0] |=  ( (2UL << GPIO_AFRL_AFSEL4_Pos) |
                        (2UL << GPIO_AFRL_AFSEL5_Pos) );

    /* ---- Steps 5 & 6: Set prescaler, period, and ARR preload -----
     * RM0383 Section 18.4.11 — TIMx_PSC
     * RM0383 Section 18.4.12 — TIMx_ARR
     * RM0383 Section 18.4.1  — TIMx_CR1, bit 7 = ARPE             */

    TIM3->PSC  = 15;     /* 16 MHz / (15+1) = 1 MHz timer clock     */
    TIM3->ARR  = 999;    /* 1 MHz  / (999+1) = 1 kHz PWM frequency  */
    TIM3->CR1 |= TIM_CR1_ARPE;   /* Enable ARR preload buffering     */

    /* ---- Step 7: Force-load PSC and ARR into active registers -----
     * RM0383 Section 18.4.6 — TIMx_EGR, bit 0 = UG (Update Generation)
     * Without this, PSC and ARR won't apply until the first overflow. */
    TIM3->EGR  = TIM_EGR_UG;

    /* ---- Step 8: Set duty cycles ----------------------------------
     * RM0383 Section 18.4.14 — TIMx_CCR1
     * RM0383 Section 18.4.15 — TIMx_CCR2                          */
    TIM3->CCR1 = 250;    /* PB4: 250/1000 = 25% duty cycle          */
    TIM3->CCR2 = 750;    /* PB5: 750/1000 = 75% duty cycle          */

    /* ---- Step 9: Configure PWM Mode 1 for CH1 and CH2 ------------
     * RM0383 Section 18.4.7 — TIMx_CCMR1
     *   OC1M  bits [6:4]   = 0b110 → PWM Mode 1, CH1
     *   OC1PE bit  [3]     = 1     → preload enable, CH1
     *   OC2M  bits [14:12] = 0b110 → PWM Mode 1, CH2
     *   OC2PE bit  [11]    = 1     → preload enable, CH2
     * Use |= to preserve any other bits in the register.            */
    TIM3->CCMR1 |= ( TIM_CCMR1_OC1PE |
                     (0b110UL << TIM_CCMR1_OC1M_Pos) |
                     TIM_CCMR1_OC2PE |
                     (0b110UL << TIM_CCMR1_OC2M_Pos) );

    /* ---- Step 10: Enable channel outputs --------------------------
     * RM0383 Section 18.4.9 — TIMx_CCER
     *   CC1E bit [0] = 1 → connect CH1 comparator output to PB4
     *   CC2E bit [4] = 1 → connect CH2 comparator output to PB5    */
    TIM3->CCER |= ( TIM_CCER_CC1E | TIM_CCER_CC2E );

    /* ---- Step 11: Start the counter — do this last ----------------
     * RM0383 Section 18.4.1 — TIMx_CR1, bit 0 = CEN               */
    TIM3->CR1 |= TIM_CR1_CEN;

    /*
     * PB4 and PB5 are now producing 1 kHz PWM in hardware.
     * The CPU does nothing for this — the timer runs autonomously.
     *
     * To change duty cycle at runtime, just write a new CCR value:
     *   TIM3->CCR1 = 500;   // PB4 → 50%
     *   TIM3->CCR2 = 100;   // PB5 → 10%
     * The preload buffer applies the change at the next period.
     */
    while (1)
    {
        /* Your application code goes here.
         * The PWM continues running without any CPU involvement. */
    }
}

Credits

Tanzimul Ittahad

1 project • 0 followers

Embedded System Engineer, Student at RUET (Bangladesh) in the Department of Electrical ans Computer Engineering

STM32 PWM in bare metal

Things used in this project

Hardware components

Software apps and online services

Hand tools and fabrication machines

Story

Mastering Bare-Metal PWM on STM32F411 (Black Pill)

Schematics

The stm32f411 Blackpill

Code

Code

Credits

Tanzimul Ittahad

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STM32 PWM in bare metal

STM32 PWM in bare metal

Things used in this project

Hardware components

Software apps and online services

Hand tools and fabrication machines

Story

Mastering Bare-Metal PWM on STM32F411 (Black Pill)

Schematics

The stm32f411 Blackpill

Code

Code

Credits

Tanzimul Ittahad

Comments

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