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*This content has been reposted with the approval of the original author.
1 PrefaceIn the process of microcontroller development, a good IDE is very important for engineers. Nowadays, the mainstream third-party IDEs includes Keil and IAR as well as Embedded Studio (commonly using J-Link parent company SEGGER’s products, yes, he also has IDE). These IDEs require a certain cost and are not good for some “sensitive” user groups. In addition, there is another reason that these IDEs started earlier, and some functions such as UI and code hints are also more “historical”.
VS Code is a free and open source modern lightweight code editor, which supports other features of almost all mainstream development languages, such as syntax highlighting, intelligent code completion, custom shortcuts, bracket matching and color discrimination, code snippets, code contrast Diff, GIT commands. It supports plug-in extension and optimizes web development and cloud application development. Only from the author’s point of view, the article shares the personal use of VSCode in the development of APM32F1 process. Due to the limited capacity of the author, the development process have mistakes inevitably, please correct. Welcome to discuss various solutions in the comments section together.
2 Environmental supportDevelopment environment of this article(Windows 10 environment):
1. VS Code installs the following plug-ins to have code completion, project setup, and debugging capabilities.
VSCode downloads:
https://code.visualstudio.com/
C / C + + plug-in (code completion support):
https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools
Cortex-Debug (simulation support):
https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug
Embedded IDE (project configuration):
https://marketplace.visualstudio.com/items?itemName=CL.eide
Chinese (Simplified) (Chinese support):
https://marketplace.visualstudio.com/items?itemName=MS-CEINTL.vscode-language-pack-zh-hans
Concerning the installation of plug-ins, not to mention here because it is easy for the partners.
2. GCC toolchain support
GNU Arm Embedded Toolchain Downloads:
https://developer.arm.com/downloads/-/gnu-rm
Here what I used is the environment variables after the installing the software of “gcc-arm-none-eabi-10.3-2021.10-win32.exe” and promoting to add to the system. If not prompting to add to the environment variables or using is full compression package, please add to the system’s environment variables by yourself. The test method is to call CMD at any place and type in the window:
arm-none-eabi-gcc -v
The corresponding gcc version number and other information will be displayed in the command line window.
3. Simulation support 01, J-Link v9 (v7.62a)
Here what I chose is the “domestic” J-Link V9 as the corresponding emulator. Its software services can be downloaded from its website:
https://www.segger.com/downloads/jlink
The latest version of the driver has supported many Geehy chips. If the old version of the driver needs to add Geehy chip support, please see my previous sharing.
4. Simulation support 02, Geehy-Link (OpenOCD)
Geehy-Link is a simulator based on CMSIS-DAP. We can also use OpenOCD for this type of simulator. If the use of the service requires us to do some operation, this part please see the follow-up content. OpenOCD can be found on its website: https://openocd.org/. Its Windows program downloads is: https://github.com/xpack-dev-tools/openocd-xpack/releases/. Since the official offer is a full package (non-installed package), we need to add it to the environment variables after the decompression to the corresponding directory.
The test method is to call CMD at any place and type in the window:
openocd -v
Information such as the corresponding OpenOCD version number is displayed in the command line window.
The chip supporting APM32F1 needs us to do some additional work, please see the following.
5. SDK package of APM32 F1
The APM32F10x standard peripheral library provided by Geehy is a tool for the development of APM32F1, which can be downloaded from its official website.
APM32F10x _ SDK _ V1.7 :
https://global.geehy.com/uploads/tool/APM32F10x_SDK_V1.7.zip
After the above environment is ready, we will use the corresponding software and hardware to complete the project creation, compilation, download and debugging functions. The main idea of VSCode development APM32F1 introduced in this article is to use GCC to compile the corresponding project code to complete a free development environment, which will involve some basic knowledge of compilation and file establishment. The following is a brief introduction to what has gone through from code to firmware (code compilation link process).
3 Compile link basisThe generation of our firmware (usually the final product is the bin file) mainly has the process of programming, compiling and linking.
Among them, we focus on the following important documents:
.c/c + + file: the code written for us, including the APM32F1 standard peripheral library code and our own code.
.s/S file: the startup file of the chip, generally including the interrupt vector number of the chip and some initialization operations before the chip starts.
.ld file: a link file of a chip, generally including the Flash size of the code store, the RAM size, and the location of some data segments.
.bin/hex file: the program content after the code is compiled and linked, in which the hex file has the corresponding address and verification information.
We need to complete the support of GCC compilation, and basically we have to prepare the corresponding. c/c + +,. s/.S,. ld file. By understanding the basic functions of each file and writing specification, we can easily write the corresponding file content (because the latest SDK APM32F1 GCC compiler support file is not yet available, we prepared this part).
3.1 Startup file writing
In the GCC environment, the chip boot file is generally used to complete chip kernel, interrupt vector number declaration, and some data segment initialization operations. Finally, the corresponding system clock initialization function (“SystemInit”function) is called in the Reset _ Handler function and then the “main” function is executed.
We create a new file “startup _ apm32f10x _ hd.S”, and its code is:
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the.data section.
defined in linker script */
.word _sidata
/* start address for the.data section. defined in linker script */
.word _sdata
/* end address for the.data section. defined in linker script */
.word _edata
/* start address for the.bss section. defined in linker script */
.word _sbss
/* end address for the.bss section. defined in linker script */
.word _ebss
/**
* [url=home.php?mod=space&uid=247401]@brief[/url] This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section.text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler,.-Reset_Handler
/**
* [url=home.php?mod=space&uid=247401]@brief[/url] This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section.text.Default_Handler, "ax", %progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler,.-Default_Handler
/*
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
**/
.section.isr_vector, "a", %progbits
.type g_pfnVectors, %object
.size g_pfnVectors,.-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDT_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCM_IRQHandler
.word EINT0_IRQHandler
.word EINT1_IRQHandler
.word EINT2_IRQHandler
.word EINT3_IRQHandler
.word EINT4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USBD_HP_CAN1_TX_IRQHandler
.word USBD_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EINT9_5_IRQHandler
.word TMR1_BRK_IRQHandler
.word TMR1_UP_IRQHandler
.word TMR1_TRG_COM_IRQHandler
.word TMR1_CC_IRQHandler
.word TMR2_IRQHandler
.word TMR3_IRQHandler
.word TMR4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EINT15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBDWakeUp_IRQHandler
.word TMR8_BRK_IRQHandler
.word TMR8_UP_IRQHandler
.word TMR8_TRG_COM_IRQHandler
.word TMR8_CC_IRQHandler
.word ADC3_IRQHandler
.word FSMC_IRQHandler
.word SDIO_IRQHandler
.word TMR5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TMR6_IRQHandler
.word TMR7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_5_IRQHandler
.word 0 // Reserved
.word USBD2_HP_CAN2_TX_IRQHandler // USBD2 High Priority or CAN2 TX
.word USBD2_LP_CAN2_RX0_IRQHandler // USBD2 Low Priority or CAN2 RX0
.word CAN2_RX1_IRQHandler // CAN2 RX1
.word CAN2_SCE_IRQHandler // CAN2 SCE
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
/*
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*/
.weak NMI_Handler
.thumb_set NMI_Handler, Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler, Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler, Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler, Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler, Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler, Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler, Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler, Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler, Default_Handler
.weak WWDT_IRQHandler
.thumb_set WWDT_IRQHandler, Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler, Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler, Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler, Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler, Default_Handler
.weak RCM_IRQHandler
.thumb_set RCM_IRQHandler, Default_Handler
.weak EINT0_IRQHandler
.thumb_set EINT0_IRQHandler, Default_Handler
.weak EINT1_IRQHandler
.thumb_set EINT1_IRQHandler, Default_Handler
.weak EINT2_IRQHandler
.thumb_set EINT2_IRQHandler, Default_Handler
.weak EINT3_IRQHandler
.thumb_set EINT3_IRQHandler, Default_Handler
.weak EINT4_IRQHandler
.thumb_set EINT4_IRQHandler, Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler, Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler, Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler, Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler, Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler, Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler, Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler, Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler, Default_Handler
.weak USBD_HP_CAN1_TX_IRQHandler
.thumb_set USBD_HP_CAN1_TX_IRQHandler, Default_Handler
.weak USBD_LP_CAN1_RX0_IRQHandler
.thumb_set USBD_LP_CAN1_RX0_IRQHandler, Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler, Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler, Default_Handler
.weak EINT9_5_IRQHandler
.thumb_set EINT9_5_IRQHandler, Default_Handler
.weak TMR1_BRK_IRQHandler
.thumb_set TMR1_BRK_IRQHandler, Default_Handler
.weak TMR1_UP_IRQHandler
.thumb_set TMR1_UP_IRQHandler, Default_Handler
.weak TMR1_TRG_COM_IRQHandler
.thumb_set TMR1_TRG_COM_IRQHandler, Default_Handler
.weak TMR1_CC_IRQHandler
.thumb_set TMR1_CC_IRQHandler, Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler, Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler, Default_Handler
.weak TMR4_IRQHandler
.thumb_set TMR4_IRQHandler, Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler, Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler, Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler, Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler, Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler, Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler, Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler, Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler, Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler, Default_Handler
.weak EINT15_10_IRQHandler
.thumb_set EINT15_10_IRQHandler, Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler, Default_Handler
.weak USBDWakeUp_IRQHandler
.thumb_set USBDWakeUp_IRQHandler, Default_Handler
.weak TMR8_BRK_IRQHandler
.thumb_set TMR8_BRK_IRQHandler, Default_Handler
.weak TMR8_UP_IRQHandler
.thumb_set TMR8_UP_IRQHandler, Default_Handler
.weak TMR8_TRG_COM_IRQHandler
.thumb_set TMR8_TRG_COM_IRQHandler, Default_Handler
.weak TMR8_CC_IRQHandler
.thumb_set TMR8_CC_IRQHandler, Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler, Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler, Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler, Default_Handler
.weak TMR5_IRQHandler
.thumb_set TMR5_IRQHandler, Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler, Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler, Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler, Default_Handler
.weak TMR6_IRQHandler
.thumb_set TMR6_IRQHandler, Default_Handler
.weak TMR7_IRQHandler
.thumb_set TMR7_IRQHandler, Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler, Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler, Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler, Default_Handler
.weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler, Default_Handler
.weak USBD2_HP_CAN2_TX_IRQHandler
.thumb_set USBD2_HP_CAN2_TX_IRQHandler, Default_Handler
.weak USBD2_LP_CAN2_RX0_IRQHandler
.thumb_set USBD2_LP_CAN2_RX0_IRQHandler, Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler, Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler, Default_Handler
3.2 Link File Writing
The link script file is generally the main storage space information of the chip and the location information of some program segments. It is also relatively simple to write it after understanding its writing specifications. Here we create a new file “apm32 _ flash.ld”, and its content is:
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20020000; /* end of 64K RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0; /* required amount of heap */
_Min_Stack_Size = 0x200; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /*.text sections (code) */
*(.text*) /*.text* sections (code) */
*(.rodata) /*.rodata sections (constants, strings, etc.) */
*(.rodata*) /*.rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext =.; /* define a global symbols at end of code */
} >FLASH
.ARM.extab : { *(.ARM.extab*.gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start =.;
*(.ARM.exidx*)
__exidx_end =.;
} >FLASH
.ARM.attributes : { *(.ARM.attributes) } > FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start =.);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end =.);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start =.);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end =.);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start =.);
KEEP (*(.fini_array*))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end =.);
} >FLASH
/* used by the startup to initialize data */
_sidata =.;
/* Initialized data sections goes into RAM, load LMA copy after code */
.data : AT ( _sidata )
{
. = ALIGN(4);
_sdata =.; /* create a global symbol at data start */
*(.data) /*.data sections */
*(.data*) /*.data* sections */
. = ALIGN(4);
_edata =.; /* define a global symbol at data end */
} >RAM
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the.bss secion */
_sbss =.; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss =.; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. =. + _Min_Heap_Size;
. =. + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
}
It is worth noticing that my link file is written based on APM32F103ZET6. If you use other chips, you need to set the size of FLASH and RAM to the size of the corresponding chip, otherwise the program will not run after downloading into the chip.
4 VSCode environment configurationAfter writing the startup and link files in the GCC environment, we then configure the VSCode environment so that we can develop smoothly on the VSCode.
4.1 Cortex-Debug plug-in configuration
Open the extension, find the Cortex-Debug plug-in, right-click “Extension Settings”, and configure the path of the corresponding tool chain. Note: After the path is copied, the file directory separator “\”is changed to “\\”.
1. Configure the Arm Toolchain path.
2. Configure JLinkGDBServer path.
3. Configure the openocd path.
4.2 Embedded IDE plug-in configuration
Open the extension, find the Embedded IDE plug-in, right-click “Extension Settings”, and configure the path of the corresponding tool chain.
1. Configure the Arm Toolchain path.
2. Configure the JLink software installation path.
3. Configure the openocd path.
If we use Geehy-Link debugging, we need to complete the support of OpenOCD for APM32F1.We build “apm32f1x.cfg”and save it to “\share\openocd\scripts\target” under the installation path of OpenOCD after editing its content.
The content of apm32f1x.cfg is:
# script for apm32f1x family
#
# apm32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME apm32f1x
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 4kB.
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1000
}
# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
set _FLASH_SIZE $FLASH_SIZE
} else {
# autodetect size
set _FLASH_SIZE 0
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# this is the SW-DP tap id not the jtag tap id
set _CPUTAPID 0x2ba01477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter speed 1000
adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event examine-end {
# DBGMCU_CR |= DBG_WWDT_STOP | DBG_IWDT_STOP |
# DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000307 0
}
$_TARGETNAME configure -event trace-config {
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
}
6 Project establishmentAfter completing the plug-in configuration of the core VSCode and the simulator configuration, we need to start writing code and establish projects. Now we have completed the overall progress of 70 %.
6.1 Prepare the source code directory
We prepare project files in a folder. Based on the “SysTick _ TimeBase”routine in “APM32F10x _ SDK _ V1.7.zip”, I create a new “VSCode” folder directly under its “Project” folder to save our project files and compile the intermediate process files.
Then we copy the “apm32 _ flash.ld” and “startup _ apm32f10x _ hd.S” files into the “VSCode” folder.
6.2 New-built project
After the source code is ready, we begin to use the “Embedded IDE” plug-in to complete our project establishment.
Then we select the new-built project path to save our project
At this time, we finally get the following directory structure.
Then we step by step to complete our source code addition, macro definition declaration, header file inclusion, link file addition and other operations.
1. Add source code, right-click “project resources”, select “virtual folder”, and add “CMSIS”, “StdPeriphDriver”, “Application” and “Board” folder directory. Then add the corresponding source file.
2. Chip configuration support, right-click on “chip support”, select install, select “From Disk”, and then select the latest official support package provided by Geehy. After the successful installation, the chip is selected as “APM32F103ZE”.
3. Select “GCC” as “Build configuration”, select “Cortex-M3” as CPU type. Link script path selects our saved path “... /apm32 _ flash.ld “(relative path selected here).
4. Select “c99” as the C standard for C/C ++ compilation in “Builder Options”.
5. Select “JLink” as “burn configuration” here. Select “APM32F103ZE” as chip name. The interface type can select “SWD” or “JTAG”, select “SWD” here. Download speed selects “8000kHz”.
If you choose to use Geehy-Link, the configuration is as follows:
6. We add the header file path of our source code and the macro definition into the “Project Properties”.
So far our project has been completed.
7 Compile and downloadAfter completing the project establishment, we can compile and download the project. Clicking on our project, we will find four icons. Each function from left to right in turn are:
Establishment, namely, compilation project.
Cleaning, namely, cleaning the compiled intermediate process file.
Download, namely, download the program to the chip (to ensure that the hardware connection is normal).
Rebuild, namely, recompile project is generally used to modify some of the source code.
First, “establishment”, view the compilation information in the terminal window.
Then “download”, the relevant download program of J-Link is called to complete the download of the chip program.
After the completion of the program compilation and download function, the function of MCU simulation is also essential.
Click the “simulation” button on the left side, enter the simulation interface, and then click the green simulation run button to enter the program simulation interface.
In the default simulation interface, there are three main sections.
The top is the control buttons of program running, such as“single-step operation”, “full-speed operation”and “exit simulation”.
The left side is the main internal information of the chip, such viewing windows as kernel registers, variable viewing, and peripheral register.
The source code is in the center. Breakpoints can be set by clicking on the left side of the line numbers
The above is the process of using VSCode to develop APM32F1, which uses some network resources only for learning, if there is infringement, please contact me to delete.
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