Clocking Wizard with Two Clocks | MMCM | Clock Buffer

Introduction

This training focuses on utilizing the PL fabric resources on the ZCU104, and it intentionally doesn’t include the Zynq MPSoC block to focus on utilizing the provided clock resources on carrier board and clocking wizard!

The design leverages the clocking resources on the ZCU104 to generate two clocks with different frequencies (100MHz and 200MHz) using the Clocking Wizard IP block.

To confirm the functionality of the generated clocks, we utilize the provided I/O and control features on the board. The design blinks two PL LEDs at different frequencies.

Finally, after downloading the bitstream to device, The PL LEDs on the carrier board will blink at different frequencies, and reset is controlled by CPU reset pushbutton.

Watch the Video on Youtube

You can watch the Video that explains the project step by step here:

Clocking on the ZCU104

• Clock Sources:
• The ZCU104 board offers multiple clock sources to meet the diverse requirements of FPGA and processing system applications.
• These include system clocks, programmable clocks, and user clocks.
• IDT Chip:
• The IDT chipset, highlighted on the image, is a one-time programmable clocksource.
• It allows for frequency adjustments via the I2C bus, providing flexibility in clock management.

• Clock Frequencies:
• The table on the slide lists various clock sources and their frequencies that provided on the carrier board. For example:
• GTY_REF_CLK: 644.53125 MHz
• HDMI_RX_REF_CLK: 156.25 MHz
• DP_REF_CLK: 270 MHz
• GTR_REF_CLK_X0_PAD: 125 MHz

For this training we are going to use provided 300MHz clock.

Controlling and I/O interfaces

The ZCU104 board provides different Controlling and I/O interfaces. This controlling I/O interfaces are used for quick change of current mode or display the current status without any extra hardware.

• The first one is the User LEDs:
• The board has four user LEDs, each located near a pushbutton.
• These LEDs are programmable and can be controlled via the PL-side or user pushbuttons.
• You can use this LEDs to show few different situations.

In our design we will have two blinking LEDs, that after downloading the bitstream they will start to blink with different frequencies. And it shows the generated clocks and everything is running properly in the P-L side.

We also use the CPU reset push button to reset the clock resources, if this push button is pressed, both LEDs will stop blinking.

Block diagram of design

• Clock Signal from the Board:
• The system receives a 300MHz clock signal from the board
• Clocking Wizard:
• The clock signal is fed into the Clocking Wizard block within the Xilinx Zynq-7000 SoC.
• The Clocking Wizard is configured to generate multiple clock signals at different frequencies.
• Generated Clock Signals:
• 100MHz Clock: This clock signal is used to drive a 27-bit counter.
• 200MHz Clock: This clock signal is used for other components, such as additional counters or logic blocks.
• Counter Blocks:
• The 27-bit counter driven by the 100MHz clock counts the clock pulses. It increments its value with each clock pulse.
• The counter’s output is a binary number that represents the count of clock pulses.
• Slice Blocks:
• Slice blocks are used to extract specific bits from the counter’s output.
• LED Control:
• The extracted bits from the slice blocks are used to control the LEDs.
• When the extracted bit is high, the corresponding LED turns on; when the bit is low, the LED turns off.

How the LEDs Blink

• Frequency of Blinking:
• The frequency at which an LED blinks is determined by the bit extracted from the counter.
• Because the input frequency of second counter is double than the first time, then the second LED will blink two time faster than the first one
• Control Mechanism:
• The reset CPU pushbutton is used to control the Clocking wizard reset. When this pushbutton is pressed, clocking wizard reset the frequencies and counters and LEDs will be stopped.

In summary, the clock signal from the board is processed by the Clocking Wizard to generate multiple clock signals. These signals drive counters, whose outputs are sliced to control the LEDs. The frequency of the LED blinking is determined by the specific bits extracted from the counter outputs.

Clocking Wizard

The LogiCORE™ IP clocking wizard is available to assist in utilizing MMCMs and PLLs to create clock networks in UltraScale architecture designs. The GUI interface is used to collect clock network parameters. The clocking wizard chooses the appropriate clock management tiles resource and optimally configures the CMT resource and associated clock routing resources.

Key Features and Benefits

• Accepts up to two input clocks and up to seven output clocks per clock network
• Automatically chooses the correct clocking primitive for a selected device and configures the clocking primitive based on user-selected clocking features
• Calculates VCO frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements
• Implements an overall configuration that supports phase shift and duty cycle requirements
• Optionally buffers clock signals

Steps to Create the Vivado Design:

• Create a New Project:
• Create a new project with ZCU104 and create a new block design for it.
• Add Programmable Differential Clock (300MHz):
• From the “Board” tab list, add a Programmable Differential Clock (300MHz). This will add a clock wizard with a differential input and connect it to the appropriate external pins.

• Add Reset:
• From the “Board” tab list, add a reset and connect it to the reset pin of the clocking wizard.

Note that when using the board examples, the board files’ pre-setups are automatically used. For example, based on the board pre-setups, the differential input is connected to I/O pins AH17 and AH18, which are connected to the 300MHz clock, and the reset input is connected to the M11 I/O pin, which is the CPU reset pushbutton.

• Configure the Clocking Wizard:
• Double-click on the clocking wizard to open it.
• The clocking wizard setup will instantiate an MMCM block to fulfill the frequency synthesis requirements.
• Set Output Frequencies:
• Go to the output tab and add two frequencies with values of 100MHz and 200MHz.
• Allow the clocking wizard to add the buffers for routing the clocks into the clock network.

• Review MMCM Setup:
• The MMCM setup tab shows automated selected setups for frequency synthesis. For example, to generate a 100MHz clock, the input clock is divided by 12 and then multiplied by 4.
• Add Counters and Slices:
• Add two counters and change them to 27 bits. Connect the clock of each counter to the clocking wizard’s outputs.

• Add two slice blocks to make the last bit of the counters as output.

• Make the slice’s outputs external pins.

Validate and Wrap Up

Validate the design and add the top wrapper.

Run Synthesis design

Run Synthesis design and Wait until the Synthesis is finished.

Open Synthesized design and then open the I/O ports, and Assign the proper pins.

set_property PACKAGE_PIN D5 [get_ports {Dout_1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Dout_1[0]}]
set_property PACKAGE_PIN D6 [get_ports {Dout_0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Dout_0[0]}]

Now you are ready to generate the bitstream!

Frequency Synthesis and clock distribution

Global Clock (GC) Pins: Clock-capable pins in Xilinx UltraScale devices are specialized pins designed to handle clock signals efficiently.

Each I/O bank contains global clock input pins to bring user clocks onto the device clock management and routing resources.

These pins have dedicated routing paths to the FPGA’s clocking resources, ensuring minimal delay and skew. This is crucial for maintaining the integrity of the clock signal across the FPGA.

These pins drive clock signals to the clock management tiles (CMTs) that contains Mixed-Mode Clock Manager (MMCM)

The Mixed-Mode Clock Manager (MMCM): MMCM) in Xilinx UltraScale FPGAs is a highly flexible and configurable clocking resource used for generating, manipulating, and distributing clock signals within the FPGA. It provides capabilities such as frequency synthesis, phase shifting, and jitter filtering, making it essential for precise timing and synchronization in high-performance designs.

Key features of the MMCM in UltraScale include:

• Frequency Synthesis: The MMCM can generate a wide range of output clock frequencies by multiplying and dividing an input clock. This allows designers to tailor the clock frequency to specific needs.
• Phase Shifting: It allows precise control over the phase of the output clock signals, which is critical for timing alignment in multi-clock domain designs.
• Jitter Filtering: The MMCM helps reduce clock jitter, improving the stability and accuracy of the clock signals.
• Multiple Outputs: The MMCM can produce multiple clock outputs, each with independently configurable frequency and phase, enabling the design to manage different clocking requirements within the FPGA.
• Dynamic Reconfiguration: It supports dynamic changes to its configuration, allowing adjustments to clock frequencies and phases during runtime without needing to reprogram the FPGA.

In UltraScale architectures, the MMCM is used in conjunction with other clocking resources like the PLL (Phase-Locked Loop) and the Global Clock Network, offering a comprehensive and robust clock management solution.

Clock buffers: Clock buffers in an FPGA play a crucial role in routing and distributing clock signals throughout the device. To distribute a clock signal to all parts of a chip with equal propagation delays, we must use specific network that is provided with FPGA fabric.

Download the bitstream to the Device

Download the bitstream into the device over the USB JTAG, you should be able to see two LEDs are blinking with different frequencies

you should also be able to reset the clock wizard by pressing CPU Rest pushbutton.