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The AUBoard from Tria is a powerful development platform built around the Artix UltraScale+™ FPGA. It provides all the essential high-speed connectivity you’d expect from a modern FPGA board, including SFP+ (up to 10 Gbps) and Gigabit Ethernet—both must-haves for networked designs. The board is also designed as a PCIe end-point, allowing it to be plugged directly into a PC or server for use as a hardware accelerator or offload engine.
For video projects, the AUBoard includes both HDMI 2.0 input and output – we’ll put the HDMI output to use in this design. The thing I like most about the AUBoard is the high-pin-count (HPC) FMC connector and Click Board™ site, giving us developers the ability to experiment with expansion modules and custom I/O. All together, these features make for a pretty versatile dev board and I’m glad to have one of these in my FPGA arsenal.
Dual-camera VideoIn this project we’re going to look at a simple video design for this board in which we connect two Raspberry Pi cameras to the AUBoard using the RPi Camera FMC. We’ll design a simple video pipeline for those cameras that will scale the images from 1080p resolution to 720x480. We’ll buffer the frames in the AUBoard’s DDR memory. On the display side we will use a Video Mixer IP to combine the two video streams and drive the HDMI TX IP to display both videos side by side on the same monitor. The whole demo will run on a bare-metal application that’s just going to setup our video and display pipelines to get everything going.
The Video PipelineThere are two of these video pipelines in the design, they are very simple and are composed of the following IP:
- MIPI CSI-2 Rx IP: Bridges the MIPI CSI-2 interface with the Raspberry Pi cameras to an AXI Stream of RAW10 pixels
- Sensor Demosaic IP: Reconstructs sub-sampled color data from Bayer image sensors. In practical terms, it converts the RAW10 pixels from the MIPI CSI-2 Rx IP to red-green-blue (RGB) values which is a convenient format for image processing.
- Gamma LUT IP: Applies a correction to the red-green-blue components to match the response of display devices.
- Video Processing Subsystem IP: Can be used for many different video processing algorithms, but in our case we’re using it as a scaler – to bring the images down in resolution so that we can fit our two video streams on a single 1080p monitor.
- Frame Buffer Write IP: Writes the video stream in frames to a memory – in our case the DDR memory.
You may have noticed that the RPi Camera FMC has four camera ports. Indeed, it does, but not all of those slots will be functional on all carrier boards. When mated with the AUBoard, there are three functional slots: CAM0, CAM2 and CAM3. We have chosen to only setup video pipelines for two of those slots, because in terms of resources, the Artix UltraScale+ device on the AUBoard can only comfortably fit two pipelines.
The Display PipelineThe diagram above illustrates our display pipeline and the elements that it is made up of. On the left of the diagram we see where our video sources are coming from: a Test Pattern Generator and two Frame Buffer Read IPs that are reading video frames left by the video pipelines. The TPG is nice to have in the design because it helps during bring-up of the video pipelines – in other words, when you’re still working on getting the video pipelines right, it allows you to test the display pipeline with a working stream. The display pipeline is composed of the following:
- Video Mixer IP: Takes in three video streams, one from the TPG and two from the Frame Buffer Reads. It combines those video streams according to how we configure it in our software.
- HDMI Tx Subsystem IP: Takes in a video stream of RGB pixels and outputs a format that is suitable for HDMI monitors.
- Video PHY Controller IP: Takes the parallel HDMI output of the HDMI Tx IP and serializes it with the GTH transceivers. HDMI 2.0 is implemented over a high-speed serial interface which allows it to support higher resolutions vs the older HDMI 1.4 which uses a parallel interface.
If you would like to reproduce this design, apart from the hardware mentioned above, you’ll need the following:
- Vivado and Vitis version 2024.1: At the time of writing, our source code works for 2024.1 – but check the repo for the latest because we regularly update our ref designs to newer versions of the tools.
- AUBoard board files: At the time of writing, the AUBoard is not contained in the Xilinx Board Store so you will need to download it from the Avnet bdf repo and manually install it.
- HDMI IP Eval license: This design uses the HDMI Tx IP which is a paid IP so in order to build the design you will at least need an evaluation license for the core. You can download one by clicking Evaluate IP from the HDMI page.
- Board file patch: If you are using AUBoard Rev 1, you will need to patch the board files – see instructions below.
Revision 1 of the AUBoard has an issue that affects designs that use the DDR4 memory and the HDMI Tx interface together. As that is precisely what we want to do, we have to patch the board files to lower the operating frequency of the DDR4 memory. We also have to add a constraint to our design to enable DCI cascading. This problem has been fixed in Revision 2 of the AUBoard, but for those of us with the Rev 1 board, we need to follow these instructions to patch the board files:
- Download the latest AUBoard board files from the Avnet bdf Git repository: https://github.com/Avnet/bdf
- To manually install the board files, copy the aub15p folder from the repo into the <vivado-install-path>\data\xhub\boards\XilinxBoardStore\boards\Xilinx folder on your local drive. The exact path may be different for your installation.
- In the files that you just copied over, locate the preset.xml file and open it in a text editor.
- Locate the following section in the file:
<ip vendor="xilinx.com" library="ip" name="ddr4">
<user_parameters>
<user_parameter name="CONFIG.C0.DDR4_MEMORYPART" value="MT40A512M16HA-083E" />
<user_parameter name="CONFIG.C0.DDR4_INPUTCLOCKPERIOD" value="3332" />
<user_parameter name="CONFIG.C0.DDR4_AXIADDRESSWIDTH" value="31" />
<user_parameter name="CONFIG.SYSTEM_CLOCK" value="Differential" />
<user_parameter name="CONFIG.C0.DDR4_DATAWIDTH" value="32" />
<user_parameter name="CONFIG.C0.DDR4_AXIDATAWIDTH" value="256" />
<user_parameter name="CONFIG.C0.DDR4_MCS_ECC" value="false" />
<user_parameter name="CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ" value="100" />
</user_parameters>
</ip>- In the line that contains INPUTCLOCKPERIOD, change the value 3332 to 3336.
- Underneath that line, add the following line:
<user_parameter name="CONFIG.C0.DDR4_TIMEPERIOD" value="938" />- Save the file.
That lowers the DDR4 operating frequency from 2400Mbps to 2133Mbps. Once you have made that modification, you're good to create projects that can use the DDR4 and HDMI Tx on the AUBoard Rev 1. Remember, you don't need these modifications if you are using a newer revision of the board.
As for the required DCI cascade constraint, we have included that in our reference design - all you have to do is to uncomment it. It looks like this in the Vivado\src\constraints\auboard.xdc file:
#set_property DCI_CASCADE {65} [get_iobanks 64]The source code for this reference design is hosted a Github repository, so the first thing you need to do is to clone the repo. I’m going to assume that you are using Windows for this build – if you are using Linux, take a look at the readme in the repo and you will find the appropriate instructions.
git clone https://github.com/fpgadeveloper/rpi-camera-fmc.gitOpen up Windows Explorer and locate the source files on your local drive. The repo contains a Vivado folder in which you will find the build-vivado.bat file. Double click on that to create the Vivado project. A terminal will open and you will be presented with a menu, allowing you to select the target board – in this case you should select the AUBoard and press ENTER.
The script will generate the Vivado project, after which you can open it in Vivado and start generating the bitstream.
Once the bitstream is generated, you can export the hardware to generate an XSA file. Make sure that the XSA file contains the bitstream.
Next step is to build the Vitis workspace which should contain a hardware platform for our design and a test application. The repo should contain a Vitis folder in which you will find a build-vitis.bat file.
Double click on that batch file and you will again be asked to select the target board. Select the AUBoard and press ENTER.
The script will generate the Vitis workspace and build the test application. When the process is complete, you can then open the workspace in Vitis Unified IDE (not Vitis Classic).
When running the build script for the first time on my Windows 10 machine, I got an error saying that the.xpfm file was not found after the platform build. This turned out to be because the path to my project was too long. I dropped the repo down to a folder named rpi in the root directory, and everything built correctly. I did not encounter this problem on my Ubuntu machine.
Prepare the Hardware- Attach the Raspberry Pi cameras to ports CAM0 and CAM2 of the RPi Camera FMC. See the FMC datasheet for more information on attaching the cameras.
- Attach the RPi Camera FMC to the AUBoard
- Connect an HDMI monitor to the HDMI TX port of the AUBoard. The HDMI TX connector is the one that is closer to the PCIe gold fingers.
- Attach the JTAG USB connector to your PC
- Open up a UART terminal on your PC (the JTAG USB connector is also a USB-UART) and set it to the comport that corresponds to the AUBoard and a speed of 115200bps
- Attach the power supply to the AUBoard
- Flip the power switch of the AUBoard to turn it ON
Since we’re now getting hands-on with the AUBoard, it’s a good time to mention some things that might save you some time by knowing.
- No boot mode switch: One atypical thing about the AUBoard is that it was not designed with a switch to set the configuration mode between JTAG and QSPI flash – instead it is hard wired for QSPI boot and when needed we simply override the current configuration using JTAG. As JTAG mode takes precedence over all other boot modes, it’s a logical choice not to include a boot switch but this is the first dev board I’ve seen that actually does not have one – so don’t waste time looking for it.
- FMC VADJ voltage is always ON: The adjustable voltage for the FMC slot is always ON (ie. you don’t need to enable it) and it is selectable between 1.2V and 1.8V through header J46. For this design we want it to be set to 1.2V – the recommended voltage for the MIPI CSI-2 Rx IP core. To set VADJ to 1.2V we must ensure that the J46 jumper is NOT POPULATED.
- Does not drive the FMC POWER GOOD signal: The AUBoard does not appear to drive the FMC PG signal which means that the RPi Camera FMC’s POWER GOOD LED will not turn ON when used with the AUBoard – even though all power rails do indeed go active after the board is powered up. I'm guessing that this will be fixed in the second revision of the AUBoard.
- In Vitis, once you have opened the workspace, select the test_app in the FLOW pane.
- Click on the Run option to launch the application on hardware via JTAG.
- In the UART terminal you should see the following debug output:
Notice that the test application lists the type of cameras that it finds attached. It is able to do this by reading from device ID registers in the image sensors via I2C. Once it has determined the type of image sensor that is attached, it is able to apply the appropriate bare-metal driver. In our case, the drivers are basic and apply a single configuration to the image sensors: 1080p resolution and a few other typical settings.
At the moment, the test application only supports two camera types:
- Raspberry Pi Camera v2
- Digilent PCam
The output on the HDMI monitor should look as shown below. Notice the grid pattern in the background of the screen - this is generated by the TPG.
In a future project, I'm going to pull the Microblaze and display pipeline out of this design and add the AXI Chip2Chip IP. My goal will be to control the video pipelines from a secondary board - the ZCU106 - via an SFP DAC cable running between the two boards at 10Gbps. From the ZCU106's PS I will setup the video pipelines on the AUBoard which will stream video over Aurora through the SFP DAC cable and into the DDR memory of the ZCU106. It's a proof-of-concept for a new FMC product that we are developing, and I think it will make for an interesting demo - so stay tuned.
As I mentioned earlier, this demo can be reproduced from the source code on the Git repository.
Revision History- 2025-11-01: First published
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