Riscduino Dual Core

Introduction

Riscduino is a Dual 32 bit RISC V-based SOC design pin-compatible to the Arduino platform and this soc is targeted for the efabless Shuttle program. This project uses only open-source toolsets for simulation, synthesis, and backend tools. The SOC flow follows the openlane methodology and the SOC environment is compatible with efabless/carvel methodology.

Riscduino Block Diagram

Key features

• Open-sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
• Dual Core 32 Bit RISC-V core
• 2KB SRAM for instruction cache
• 2KB SRAM for data cache
• 2KB SRAM for Tightly coupled memory - For Data Memory
• Quad SPI Master
• UART with 16Byte FIFO
• USB 1.1 Host
• I2C Master
• Simple SPI Master
• 6 Channel ADC (in Progress)
• 6 PWM
• Pin Compatible to Arduino Uno
• Wishbone compatible design
• Written in System Verilog
• Open-source toolset
• simulation - iverilog
• synthesis - yosys
• backend/sta - openlane tool set

SOC Pin Mapping

Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arduino.

RISC V Core

Riscduino SOC Integrated Dual 32 Bits RISC V core. The initial version of the single-core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)

RISC V core customization for Riscduino SOC

The following Design changes are done on the basic version of syntacore RISC core.

• Some of the sv syntex is changed to standard Verilog format to make itcompatible with opensource tool iverilog & yosys
• Local Instruction Memory depth increased from 4 to 8 location
• Instruction Mem Request is changed from Single word to 4 Word Burst
• Multiplication and Division are changed to improve timing
• Additional pipe line stages were added to improve the RISC timing closure near to 50Mhz
• 2KB instruction cache
• 2KB data cache
• Additional routers is added towards the instruction cache
• Additional routers are added towards data cache
• Dual-core related changes
• Modified AXI/AHB interface to wishbone interface for instruction and data memory interface

Block Diagram

RISC V Core Key feature

• RV32I or RV32E ISA base + optional RVM and RVC standard extensions
• Machine privilege mode only
• 2 to 5 stage pipeline
• 2KB icache
• 2KB dcache
• Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
• Optional RISC-V Debug subsystem with JTAG interface
• Optional on-chip Tightly-Coupled Memory

SOC Memory Map

SOC Size

SOC Register Map

• Register Map: Wishbone HOST

• Register: GLBL_CTRL

• Register: BANK_CTRL

• Register: CLK_SKEW_CTRL1

• Register Map: SPI MASTER

• Register: GLBL_CTRL

• Register: DMEM_CTRL1

• Register: DMEM_CTRL2

• Register: IMEM_CTRL1

• Register: IMEM_CTRL2

• Register: IMEM_ADDR

• Register: IMEM_WDATA

• Register: IMEM_RDATA

• Register: SPI_STATUS

• Register Map: Global Register

• Register: RISC_FUSE

• Register: INTR_CTRL

Links

• EFabless MPW-5 Project - https://platform.efabless.com/projects/718
• Github Repo - https://github.com/dineshannayya/riscduino_dcore/blob/main/README.md

This project was created by Dinesh Annayya, and we are sharing it here to help spread the word about the EFabless Open MPW Shuttle Program.