Published April 6, 2018 © Apache-2.0

Logic Analyzer

This project consists of making a logical analyzer, which can help us analyze digital hardware and software analysis.

IntermediateWork in progress1,104

Things used in this project

Hardware components

Digilent Cmod A7-35T: Breadboardable Artix-7 FPGA Module

Digilent Pmod RS232

Software apps and online services

LabVIEW Community Edition

Story

Project Description

This project consists of making a logical analyzer, which can help us analyze digital hardware, project verification and integration of software analysis. The logical analyzers are usually made of 34 and 136 channels, each channel has a single digital signal. It does not measure analog details, but instead detects levels of logic thresholds.

We use the logic analyzer to be able to:

Trigger and check the operation of the digital system;

Track and correct multiple digital signals simultaneously;

Detect and analyze sync errors;

Track the execution of embedded software.

Using the LabView project system, we will transmit a sequence of 11 bits serially via the RS-232 interface. Those 11 bits have the following meaning: the first bit is the start bit value (0 logic), the next 8 bits are the data bits, the penultimate bit represents the parity bit and the last bit represents the stop bit (1 logic) which indicates the end of receiving a byte. The logical analyzer consists of 3 large sub-blocks: the block of registers, the FIFO memory block and the logical block of acquisition.

Block of Registers

The block of registers are also made office sub-blocks:

The address register consists of 8 D-type bistabs, connected to a common clock signal; it should be analyzed along with the address decoder because it's like a buffer which has the role of sending the data to the address decoder so that data can be interpreted. At the level of the decoder we have an exit which, when the 0 logic signal is given, it begins to decode the received data. It works on two bits;

The command register activates when it receives a clock signal from the address decoder. At the input we have 8 bits of data and at the output we have 6 bits, the first 4 bits represent the ROM entry (sets the sampling frequency) and the next 2 bits are input bits for the data acquisition logic;

The control register sets the mode and trigger type;

The status register consists of 2 D-type bistabs with 3 entries. By the first input the register receives the clock signal from the acquisition logic, starting to work.

The other two entries have the following meaning: one of the bits signals that the FIFO data memory is empty, which means that the data will be transmitted by the status register to an analyzer output. The other bit has the main role of resetting this registry after a full purchase has been made.

The register who orders the acquisition logic has as inputs those 8 data bits and a clock signal, given by the address decoder.

Logic Block of Acquisition

The logic block of acquisition has the primary role of determining the number of bits of the received data sequence. This function is performed with a numerator and a 2x4 multiplexer. According to the communication parameters we have a number of 16, 32, 64 or 128 samples of input data. Depending on the number of samples selected, the counter will count up to that value, then using the multiplexer will display a signal indicating that a complete purchase has been made.

FIFO Memory Block

The FIFO memory block has a FIFO memory as the primary element (First In, First Out). It has the role of memorizing a data set (it can store up to 128 bytes). In addition to this memory, it also contains two blocks: one consisting of "AND" gates and one consisting of 8x1 multiplexers. The sub-block consisting of 8 logical "AND" has the role of letting the information pass, or to block its arrival in FIFO memory, based on a signal. The block of multiplexers is designed to sort out which information will reach the transmission block, the set of bytes in FIFO memory, and if the memory is empty, based on a signal given by the register block, will start transmitting the data from the status register.

Communication with the PC is done using the RS-232 serial interface and the LabView software. At the serial RS-232 interface, the transmission and reception is bit-bitted, requiring only one thread for transmission. RS-232 is a standard, in the sense that all computer models and most measuring instruments incorporate them. Serial data can be sent synchronously (clocked) or asynchronously (clocked). This interface has two types of connectors available: DB25S and DB9S. The first ensures the total functionality of the interface while the second provides a minimal space for the smaller instrumentation in dimensions.

The signals of this interface are divided into 3 categories:

data (TxD, RxD). There are two data channels that allow full-duplex communication (bidirectional);

Communication control (RTS, CTS). These signals provide the support through which data traffic is controlled.

timing (TC, RC). For synchronous communications, it is necessary to transmit attract signal to synchronize the receiver with the transmitter.

The data is transmitted as packets, each representing a single ASCII character and containing sufficient information to be decoded without the help of a tact signal.

LabVIEW is a graphical programming language that uses block diagrams to create applications. With this software we can display the data, where you can see and interpret the resulting waveforms. These applications are built to control and acquire data, analyze them and present results. In the graphical programming environment provided by LabVIEW, the virtual tool defines a program that consists of a user-interface, the front panel and a block schema program.

Block Codes

Block Memory
module fifomemory(A, 
                  B, 
                  BLOCARE, 
                  RDCLOCK, 
                  RDEN, 
                  RST, 
                  SEL, 
                  WRCLOCK, 
                  WREN, 
                  EMPTY, 
                  FULL, 
                  Y);

    input [7:0] A;
    input [7:0] B;
    input BLOCARE;
    input RDCLOCK;
    input RDEN;
    input RST;
    input SEL;
    input WRCLOCK;
    input WREN;
   output EMPTY;
   output FULL;
   output [7:0] Y;
   
   wire [15:0] I;
   wire [15:0] N;
   wire [1:0] XLXN_32;
   
   optsi  XLXI_1 (.A(A[7:0]), 
                 .BLOCARE(BLOCARE), 
                 .Y(I[7:0]));
   mux2la1  XLXI_2 (.A(SEL), 
                   .B(B[7:0]), 
                   .C(N[7:0]), 
                   .Y(Y[7:0]));
   GND  XLXI_13_8 (.G(I[8]));
   GND  XLXI_13_9 (.G(I[9]));
   GND  XLXI_13_10 (.G(I[10]));
   GND  XLXI_13_11 (.G(I[11]));
   GND  XLXI_13_12 (.G(I[12]));
   GND  XLXI_13_13 (.G(I[13]));
   GND  XLXI_13_14 (.G(I[14]));
   GND  XLXI_13_15 (.G(I[15]));
   GND  XLXI_17_0 (.G(XLXN_32[0]));
   GND  XLXI_17_1 (.G(XLXN_32[1]));
   FIFO18 #( .DATA_WIDTH(9), .FIRST_WORD_FALL_THROUGH("FALSE"), .DO_REG(1), 
         .ALMOST_FULL_OFFSET(12'h080), .ALMOST_EMPTY_OFFSET(12'h080), 
         .EN_SYN("FALSE") ) XLXI_19 (.DI(I[15:0]), 
                   .DIP(XLXN_32[1:0]), 
                   .RDCLK(RDCLOCK), 
                   .RDEN(RDEN), 
                   .RST(RST), 
                   .WRCLK(WRCLOCK), 
                   .WREN(WREN), 
                   .ALMOSTEMPTY(), 
                   .ALMOSTFULL(), 
                   .DO(N[15:0]), 
                   .DOP(), 
                   .EMPTY(EMPTY), 
                   .FULL(FULL), 
                   .RDCOUNT(), 
                   .RDERR(), 
                   .WRCOUNT(), 
                   .WRERR());
endmodule


Block with sampling rates

module OR12_HXILINX_genbr (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11);
    

   output O;

   input I0;
   input I1;
   input I2;
   input I3;
   input I4;
   input I5;
   input I6;
   input I7;
   input I8;
   input I9;
   input I10;
   input I11;

assign O = (I0 || I1 || I2 || I3 || I4 || I5 || I6 || I7 || I8 || I9 || I10 || I11 );

endmodule
`timescale 100 ps / 10 ps

module FJKC_HXILINX_genbr(Q, C, CLR, J, K);
   
   output             Q;

   input 	      C;	
   input 	      CLR;	
   input              J;
   input              K;
   
   parameter INIT = 1'b0;
   reg                Q = INIT;


   always @(posedge C or posedge CLR)
     begin
	if (CLR)
	  Q <= 1'b0;
	else
        begin
           if(!J)
           begin
              if(K)
              Q <= 1'b0;
           end
           else
           begin
              if(!K)
              Q <= 1'b1;
              else 
              Q <= !Q;
           end
        end
     end
   
endmodule
`timescale 1ns / 1ps

module div10_MUSER_genbr(Clk, 
                         Q0, 
                         Q1, 
                         Q2, 
                         Q3);

    input Clk;
   output Q0;
   output Q1;
   output Q2;
   output Q3;
   
   wire XLXN_1;
   wire XLXN_2;
   wire XLXN_4;
   wire XLXN_5;
   wire XLXN_23;
   wire XLXN_31;
   wire Q0_DUMMY;
   wire Q1_DUMMY;
   wire Q2_DUMMY;
   wire Q3_DUMMY;
   
   assign Q0 = Q0_DUMMY;
   assign Q1 = Q1_DUMMY;
   assign Q2 = Q2_DUMMY;
   assign Q3 = Q3_DUMMY;
   (* HU_SET = "XLXI_1_0" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_1 (.C(XLXN_31), 
                              .CLR(), 
                              .J(XLXN_1), 
                              .K(XLXN_1), 
                              .Q(Q0_DUMMY));
   VCC  XLXI_2 (.P(XLXN_1));
   (* HU_SET = "XLXI_3_1" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_3 (.C(XLXN_31), 
                              .CLR(), 
                              .J(XLXN_5), 
                              .K(Q0_DUMMY), 
                              .Q(Q3_DUMMY));
   (* HU_SET = "XLXI_4_2" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_4 (.C(XLXN_31), 
                              .CLR(), 
                              .J(XLXN_2), 
                              .K(Q0_DUMMY), 
                              .Q(Q1_DUMMY));
   AND2  XLXI_5 (.I0(Q0_DUMMY), 
                .I1(XLXN_23), 
                .O(XLXN_2));
   (* HU_SET = "XLXI_6_3" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_6 (.C(XLXN_31), 
                              .CLR(), 
                              .J(XLXN_4), 
                              .K(XLXN_4), 
                              .Q(Q2_DUMMY));
   AND2  XLXI_7 (.I0(Q0_DUMMY), 
                .I1(Q1_DUMMY), 
                .O(XLXN_4));
   AND3  XLXI_8 (.I0(Q0_DUMMY), 
                .I1(Q2_DUMMY), 
                .I2(Q1_DUMMY), 
                .O(XLXN_5));
   INV  XLXI_11 (.I(Q3_DUMMY), 
                .O(XLXN_23));
   INV  XLXI_14 (.I(Clk), 
                .O(XLXN_31));
endmodule
`timescale 1ns / 1ps

module div15_MUSER_genbr(Clk, 
                         Q0, 
                         Q1, 
                         Q2, 
                         Q3);

    input Clk;
   output Q0;
   output Q1;
   output Q2;
   output Q3;
   
   wire XLXN_1;
   wire XLXN_7;
   wire XLXN_8;
   wire XLXN_9;
   wire XLXN_12;
   wire XLXN_13;
   wire XLXN_14;
   wire XLXN_21;
   wire XLXN_22;
   wire XLXN_26;
   wire XLXN_28;
   wire XLXN_29;
   wire XLXN_30;
   wire Q0_DUMMY;
   wire Q1_DUMMY;
   wire Q2_DUMMY;
   wire Q3_DUMMY;
   
   assign Q0 = Q0_DUMMY;
   assign Q1 = Q1_DUMMY;
   assign Q2 = Q2_DUMMY;
   assign Q3 = Q3_DUMMY;
   (* HU_SET = "XLXI_1_4" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_1 (.C(Clk), 
                              .CLR(), 
                              .J(XLXN_26), 
                              .K(XLXN_1), 
                              .Q(Q0_DUMMY));
   (* HU_SET = "XLXI_2_5" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_2 (.C(Clk), 
                              .CLR(), 
                              .J(Q0_DUMMY), 
                              .K(XLXN_9), 
                              .Q(Q1_DUMMY));
   (* HU_SET = "XLXI_3_6" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_3 (.C(Clk), 
                              .CLR(), 
                              .J(XLXN_12), 
                              .K(XLXN_14), 
                              .Q(Q2_DUMMY));
   (* HU_SET = "XLXI_4_7" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_4 (.C(Clk), 
                              .CLR(), 
                              .J(XLXN_22), 
                              .K(XLXN_21), 
                              .Q(Q3_DUMMY));
   VCC  XLXI_5 (.P(XLXN_1));
   AND2  XLXI_6 (.I0(Q0_DUMMY), 
                .I1(Q1_DUMMY), 
                .O(XLXN_7));
   AND2  XLXI_7 (.I0(Q2_DUMMY), 
                .I1(Q3_DUMMY), 
                .O(XLXN_8));
   OR2  XLXI_8 (.I0(XLXN_7), 
               .I1(XLXN_8), 
               .O(XLXN_9));
   AND2  XLXI_9 (.I0(Q1_DUMMY), 
                .I1(Q0_DUMMY), 
                .O(XLXN_12));
   AND2  XLXI_10 (.I0(Q1_DUMMY), 
                 .I1(Q3_DUMMY), 
                 .O(XLXN_13));
   OR2  XLXI_11 (.I0(XLXN_12), 
                .I1(XLXN_13), 
                .O(XLXN_14));
   AND2  XLXI_12 (.I0(Q2_DUMMY), 
                 .I1(Q1_DUMMY), 
                 .O(XLXN_21));
   AND3  XLXI_13 (.I0(Q2_DUMMY), 
                 .I1(Q1_DUMMY), 
                 .I2(Q0_DUMMY), 
                 .O(XLXN_22));
   INV  XLXI_14 (.I(Q1_DUMMY), 
                .O(XLXN_30));
   INV  XLXI_15 (.I(Q2_DUMMY), 
                .O(XLXN_29));
   INV  XLXI_16 (.I(Q3_DUMMY), 
                .O(XLXN_28));
   OR3  XLXI_17 (.I0(XLXN_30), 
                .I1(XLXN_29), 
                .I2(XLXN_28), 
                .O(XLXN_26));
endmodule
`timescale 1ns / 1ps

module div8_MUSER_genbr(Clk, 
                        Q0, 
                        Q1, 
                        Q2);

    input Clk;
   output Q0;
   output Q1;
   output Q2;
   
   wire XLXN_6;
   wire XLXN_7;
   wire Q0_DUMMY;
   wire Q1_DUMMY;
   
   assign Q0 = Q0_DUMMY;
   assign Q1 = Q1_DUMMY;
   (* HU_SET = "XLXI_1_8" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_1 (.C(Clk), 
                              .CLR(), 
                              .J(XLXN_7), 
                              .K(XLXN_7), 
                              .Q(Q0_DUMMY));
   (* HU_SET = "XLXI_2_9" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_2 (.C(Clk), 
                              .CLR(), 
                              .J(Q0_DUMMY), 
                              .K(Q0_DUMMY), 
                              .Q(Q1_DUMMY));
   (* HU_SET = "XLXI_3_10" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_3 (.C(Clk), 
                              .CLR(), 
                              .J(XLXN_6), 
                              .K(XLXN_6), 
                              .Q(Q2));
   AND2  XLXI_4 (.I0(Q1_DUMMY), 
                .I1(Q0_DUMMY), 
                .O(XLXN_6));
   VCC  XLXI_7 (.P(XLXN_7));
endmodule
`timescale 1ns / 1ps

module div2_MUSER_genbr(Clk, 
                        Q0);

    input Clk;
   output Q0;
   
   wire XLXN_15;
   
   (* HU_SET = "XLXI_3_11" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_3 (.C(Clk), 
                              .CLR(), 
                              .J(XLXN_15), 
                              .K(XLXN_15), 
                              .Q(Q0));
   VCC  XLXI_9 (.P(XLXN_15));
endmodule
`timescale 1ns / 1ps

module div625_MUSER_genbr(Clk, 
                          HZ625, 
                          KHz6, 
                          KHz93, 
                          KHz750, 
                          MHz6);

    input Clk;
   output HZ625;
   output KHz6;
   output KHz93;
   output KHz750;
   output MHz6;
   
   wire XLXN_3;
   wire XLXN_5;
   wire XLXN_8;
   wire MHz6_DUMMY;
   wire KHz750_DUMMY;
   wire KHz93_DUMMY;
   wire KHz6_DUMMY;
   
   assign KHz6 = KHz6_DUMMY;
   assign KHz93 = KHz93_DUMMY;
   assign KHz750 = KHz750_DUMMY;
   assign MHz6 = MHz6_DUMMY;
   div2_MUSER_genbr  XLXI_1 (.Clk(Clk), 
                            .Q0(MHz6_DUMMY));
   div8_MUSER_genbr  XLXI_2 (.Clk(XLXN_3), 
                            .Q0(), 
                            .Q1(KHz750_DUMMY), 
                            .Q2());
   div15_MUSER_genbr  XLXI_4 (.Clk(XLXN_8), 
                             .Q0(), 
                             .Q1(), 
                             .Q2(KHz6_DUMMY), 
                             .Q3());
   div10_MUSER_genbr  XLXI_6 (.Clk(KHz6_DUMMY), 
                             .Q0(), 
                             .Q1(HZ625), 
                             .Q2(), 
                             .Q3());
   div8_MUSER_genbr  XLXI_7 (.Clk(XLXN_5), 
                            .Q0(), 
                            .Q1(KHz93_DUMMY), 
                            .Q2());
   INV  XLXI_8 (.I(MHz6_DUMMY), 
               .O(XLXN_3));
   INV  XLXI_9 (.I(KHz750_DUMMY), 
               .O(XLXN_5));
   INV  XLXI_10 (.I(KHz93_DUMMY), 
                .O(XLXN_8));
endmodule
`timescale 1ns / 1ps

module mux_MUSER_genbr(A0, 
                       A1, 
                       A2, 
                       A3, 
                       Y0, 
                       Y1, 
                       Y2, 
                       Y3, 
                       Y4, 
                       Y5, 
                       Y6, 
                       Y7, 
                       Y8, 
                       Y9, 
                       Y10, 
                       Y11, 
                       Q);

    input A0;
    input A1;
    input A2;
    input A3;
    input Y0;
    input Y1;
    input Y2;
    input Y3;
    input Y4;
    input Y5;
    input Y6;
    input Y7;
    input Y8;
    input Y9;
    input Y10;
    input Y11;
   output Q;
   
   wire XLXN_17;
   wire XLXN_18;
   wire XLXN_19;
   wire XLXN_22;
   wire XLXN_30;
   wire XLXN_32;
   wire XLXN_36;
   wire XLXN_37;
   wire XLXN_39;
   wire XLXN_40;
   wire XLXN_41;
   wire XLXN_47;
   wire XLXN_48;
   wire XLXN_50;
   wire XLXN_51;
   wire XLXN_79;
   
   INV  XLXI_2 (.I(A3), 
               .O(XLXN_22));
   INV  XLXI_3 (.I(A2), 
               .O(XLXN_19));
   INV  XLXI_4 (.I(A1), 
               .O(XLXN_18));
   INV  XLXI_5 (.I(A0), 
               .O(XLXN_17));
   (* HU_SET = "XLXI_18_12" *) 
   OR12_HXILINX_genbr  XLXI_18 (.I0(XLXN_30), 
                               .I1(XLXN_51), 
                               .I2(XLXN_32), 
                               .I3(XLXN_50), 
                               .I4(XLXN_79), 
                               .I5(XLXN_48), 
                               .I6(XLXN_36), 
                               .I7(XLXN_37), 
                               .I8(XLXN_47), 
                               .I9(XLXN_39), 
                               .I10(XLXN_40), 
                               .I11(XLXN_41), 
                               .O(Q));
   AND5  XLXI_19 (.I0(XLXN_22), 
                 .I1(XLXN_19), 
                 .I2(XLXN_17), 
                 .I3(XLXN_18), 
                 .I4(Y0), 
                 .O(XLXN_41));
   AND5  XLXI_20 (.I0(A0), 
                 .I1(XLXN_18), 
                 .I2(XLXN_19), 
                 .I3(XLXN_22), 
                 .I4(Y1), 
                 .O(XLXN_40));
   AND5  XLXI_21 (.I0(XLXN_19), 
                 .I1(XLXN_22), 
                 .I2(XLXN_17), 
                 .I3(A1), 
                 .I4(Y2), 
                 .O(XLXN_39));
   AND5  XLXI_23 (.I0(Y3), 
                 .I1(A0), 
                 .I2(A1), 
                 .I3(XLXN_19), 
                 .I4(XLXN_22), 
                 .O(XLXN_47));
   AND5  XLXI_24 (.I0(Y4), 
                 .I1(XLXN_17), 
                 .I2(XLXN_18), 
                 .I3(XLXN_22), 
                 .I4(A2), 
                 .O(XLXN_37));
   AND5  XLXI_26 (.I0(Y5), 
                 .I1(XLXN_18), 
                 .I2(XLXN_22), 
                 .I3(A0), 
                 .I4(A2), 
                 .O(XLXN_36));
   AND5  XLXI_27 (.I0(A2), 
                 .I1(A1), 
                 .I2(XLXN_17), 
                 .I3(XLXN_22), 
                 .I4(Y6), 
                 .O(XLXN_48));
   AND5  XLXI_28 (.I0(Y7), 
                 .I1(A0), 
                 .I2(A1), 
                 .I3(A2), 
                 .I4(XLXN_22), 
                 .O(XLXN_79));
   AND5  XLXI_29 (.I0(XLXN_19), 
                 .I1(XLXN_18), 
                 .I2(XLXN_17), 
                 .I3(Y8), 
                 .I4(A3), 
                 .O(XLXN_51));
   AND5  XLXI_30 (.I0(Y9), 
                 .I1(A3), 
                 .I2(A0), 
                 .I3(XLXN_18), 
                 .I4(XLXN_19), 
                 .O(XLXN_50));
   AND5  XLXI_31 (.I0(Y10), 
                 .I1(A1), 
                 .I2(A3), 
                 .I3(XLXN_19), 
                 .I4(XLXN_17), 
                 .O(XLXN_32));
   AND5  XLXI_32 (.I0(Y11), 
                 .I1(A0), 
                 .I2(A1), 
                 .I3(A3), 
                 .I4(XLXN_19), 
                 .O(XLXN_30));
endmodule
`timescale 1ns / 1ps

module div5_MUSER_genbr(CLK, 
                        Q0, 
                        Q1, 
                        Q2);

    input CLK;
   output Q0;
   output Q1;
   output Q2;
   
   wire XLXN_9;
   wire XLXN_10;
   wire XLXN_12;
   wire XLXN_14;
   wire Q0_DUMMY;
   wire Q1_DUMMY;
   wire Q2_DUMMY;
   
   assign Q0 = Q0_DUMMY;
   assign Q1 = Q1_DUMMY;
   assign Q2 = Q2_DUMMY;
   (* HU_SET = "XLXI_2_13" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_2 (.C(CLK), 
                              .CLR(), 
                              .J(XLXN_12), 
                              .K(XLXN_9), 
                              .Q(Q0_DUMMY));
   (* HU_SET = "XLXI_3_14" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_3 (.C(CLK), 
                              .CLR(), 
                              .J(Q0_DUMMY), 
                              .K(Q0_DUMMY), 
                              .Q(Q1_DUMMY));
   (* HU_SET = "XLXI_4_15" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_4 (.C(CLK), 
                              .CLR(), 
                              .J(XLXN_14), 
                              .K(XLXN_10), 
                              .Q(Q2_DUMMY));
   AND2  XLXI_5 (.I0(Q1_DUMMY), 
                .I1(Q0_DUMMY), 
                .O(XLXN_14));
   VCC  XLXI_8 (.P(XLXN_9));
   VCC  XLXI_9 (.P(XLXN_10));
   INV  XLXI_13 (.I(Q2_DUMMY), 
                .O(XLXN_12));
endmodule
`timescale 1ns / 1ps

module div3_MUSER_genbr(CLK, 
                        Q0, 
                        Q1);

    input CLK;
   output Q0;
   output Q1;
   
   wire XLXN_4;
   wire XLXN_7;
   wire Q0_DUMMY;
   wire Q1_DUMMY;
   
   assign Q0 = Q0_DUMMY;
   assign Q1 = Q1_DUMMY;
   (* HU_SET = "XLXI_3_16" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_3 (.C(CLK), 
                              .CLR(), 
                              .J(XLXN_7), 
                              .K(XLXN_4), 
                              .Q(Q0_DUMMY));
   (* HU_SET = "XLXI_4_17" *) 
   FJKC_HXILINX_genbr #( .INIT(1'b0) ) XLXI_4 (.C(CLK), 
                              .CLR(), 
                              .J(Q0_DUMMY), 
                              .K(XLXN_4), 
                              .Q(Q1_DUMMY));
   VCC  XLXI_5 (.P(XLXN_4));
   INV  XLXI_6 (.I(Q1_DUMMY), 
               .O(XLXN_7));
endmodule
`timescale 1ns / 1ps

module divizor12_MUSER_genbr(A, 
                             I1, 
                             HZ100, 
                             HZ500, 
                             KHZ1, 
                             KHZ5, 
                             KHZ10, 
                             KHZ50, 
                             KHZ100, 
                             KHZ500, 
                             MHZ1, 
                             MHZ2, 
                             MHZ6, 
                             Y);

    input [3:0] A;
    input I1;
   output HZ100;
   output HZ500;
   output KHZ1;
   output KHZ5;
   output KHZ10;
   output KHZ50;
   output KHZ100;
   output KHZ500;
   output MHZ1;
   output MHZ2;
   output MHZ6;
   output Y;
   
   wire KHZ50_DUMMY;
   wire HZ500_DUMMY;
   wire KHZ1_DUMMY;
   wire KHZ5_DUMMY;
   wire KHZ10_DUMMY;
   wire KHZ500_DUMMY;
   wire HZ100_DUMMY;
   wire MHZ1_DUMMY;
   wire MHZ2_DUMMY;
   wire MHZ6_DUMMY;
   wire KHZ100_DUMMY;
   
   assign HZ100 = HZ100_DUMMY;
   assign HZ500 = HZ500_DUMMY;
   assign KHZ1 = KHZ1_DUMMY;
   assign KHZ5 = KHZ5_DUMMY;
   assign KHZ10 = KHZ10_DUMMY;
   assign KHZ50 = KHZ50_DUMMY;
   assign KHZ100 = KHZ100_DUMMY;
   assign KHZ500 = KHZ500_DUMMY;
   assign MHZ1 = MHZ1_DUMMY;
   assign MHZ2 = MHZ2_DUMMY;
   assign MHZ6 = MHZ6_DUMMY;
   div2_MUSER_genbr  XLXI_1 (.Clk(I1), 
                            .Q0(MHZ6_DUMMY));
   div3_MUSER_genbr  XLXI_2 (.CLK(MHZ6_DUMMY), 
                            .Q0(), 
                            .Q1(MHZ2_DUMMY));
   div2_MUSER_genbr  XLXI_4 (.Clk(MHZ2_DUMMY), 
                            .Q0(MHZ1_DUMMY));
   div2_MUSER_genbr  XLXI_5 (.Clk(MHZ1_DUMMY), 
                            .Q0(KHZ500_DUMMY));
   div5_MUSER_genbr  XLXI_22 (.CLK(KHZ500_DUMMY), 
                             .Q0(), 
                             .Q1(), 
                             .Q2(KHZ100_DUMMY));
   div2_MUSER_genbr  XLXI_25 (.Clk(KHZ10_DUMMY), 
                             .Q0(KHZ5_DUMMY));
   div5_MUSER_genbr  XLXI_26 (.CLK(KHZ5_DUMMY), 
                             .Q0(), 
                             .Q1(), 
                             .Q2(KHZ1_DUMMY));
   div2_MUSER_genbr  XLXI_27 (.Clk(KHZ1_DUMMY), 
                             .Q0(HZ500_DUMMY));
   div5_MUSER_genbr  XLXI_28 (.CLK(HZ500_DUMMY), 
                             .Q0(), 
                             .Q1(), 
                             .Q2(HZ100_DUMMY));
   div5_MUSER_genbr  XLXI_29 (.CLK(KHZ50_DUMMY), 
                             .Q0(), 
                             .Q1(), 
                             .Q2(KHZ10_DUMMY));
   div2_MUSER_genbr  XLXI_30 (.Clk(KHZ100_DUMMY), 
                             .Q0(KHZ50_DUMMY));
   mux_MUSER_genbr  XLXI_31 (.A0(A[0]), 
                            .A1(A[1]), 
                            .A2(A[2]), 
                            .A3(A[3]), 
                            .Y0(I1), 
                            .Y1(MHZ6_DUMMY), 
                            .Y2(MHZ2_DUMMY), 
                            .Y3(MHZ1_DUMMY), 
                            .Y4(KHZ500_DUMMY), 
                            .Y5(KHZ100_DUMMY), 
                            .Y6(KHZ50_DUMMY), 
                            .Y7(KHZ10_DUMMY), 
                            .Y8(KHZ5_DUMMY), 
                            .Y9(KHZ1_DUMMY), 
                            .Y10(HZ500_DUMMY), 
                            .Y11(HZ100_DUMMY), 
                            .Q(Y));
endmodule
`timescale 1ns / 1ps

module genbr(CLK, 
             RX, 
             BRI, 
             CLK_ES);

    input CLK;
    input [3:0] RX;
   output BRI;
   output CLK_ES;
   
   wire XLXN_3;
   wire XLXN_4;
   wire XLXN_5;
   wire XLXN_6;
   
   divizor12_MUSER_genbr  XLXI_5 (.A(RX[3:0]), 
                                 .I1(CLK), 
                                 .HZ100(), 
                                 .HZ500(), 
                                 .KHZ1(), 
                                 .KHZ5(), 
                                 .KHZ10(), 
                                 .KHZ50(), 
                                 .KHZ100(), 
                                 .KHZ500(), 
                                 .MHZ1(), 
                                 .MHZ2(), 
                                 .MHZ6(), 
                                 .Y(CLK_ES));
   div625_MUSER_genbr  XLXI_10 (.Clk(CLK), 
                               .HZ625(BRI), 
                               .KHz6(XLXN_6), 
                               .KHz93(XLXN_5), 
                               .KHz750(XLXN_4), 
                               .MHz6(XLXN_3));
endmodule

The block of registers 


module decodif_MUSER_registri(D, 
                              Y0, 
                              Y1, 
                              Y2, 
                              Y3);

    input [3:0] D;
   output Y0;
   output Y1;
   output Y2;
   output Y3;
   
   wire XLXN_6;
   wire XLXN_9;
   wire XLXN_11;
   wire XLXN_15;
   
   INV  XLXI_1 (.I(D[0]), 
               .O(XLXN_11));
   INV  XLXI_2 (.I(D[1]), 
               .O(XLXN_6));
   INV  XLXI_3 (.I(D[2]), 
               .O(XLXN_9));
   INV  XLXI_4 (.I(D[3]), 
               .O(XLXN_15));
   AND4  XLXI_5 (.I0(XLXN_11), 
                .I1(XLXN_6), 
                .I2(XLXN_9), 
                .I3(XLXN_15), 
                .O(Y0));
   AND4  XLXI_6 (.I0(XLXN_9), 
                .I1(XLXN_6), 
                .I2(XLXN_11), 
                .I3(D[3]), 
                .O(Y1));
   AND4  XLXI_7 (.I0(XLXN_15), 
                .I1(D[3]), 
                .I2(XLXN_6), 
                .I3(XLXN_11), 
                .O(Y2));
   AND4  XLXI_8 (.I0(D[3]), 
                .I1(D[2]), 
                .I2(XLXN_6), 
                .I3(XLXN_11), 
                .O(Y3));
endmodule
`timescale 1ns / 1ps

module decra_MUSER_registri(D, 
                            MEMA, 
                            CitireStare, 
                            MEMc, 
                            MEMfe, 
                            MEMRK);

    input [7:0] D;
    input MEMA;
   output CitireStare;
   output MEMc;
   output MEMfe;
   output MEMRK;
   
   wire XLXN_1;
   wire XLXN_2;
   wire XLXN_3;
   wire XLXN_4;
   wire XLXN_5;
   wire [7:0] D_DUMMY;
   
   assign D_DUMMY[7:0] = D[7:0];
   FDC #( .INIT(1'b0) ) XLXI_1 (.C(XLXN_1), 
               .CLR(), 
               .D(XLXN_2), 
               .Q(MEMRK));
   FDC #( .INIT(1'b0) ) XLXI_2 (.C(XLXN_1), 
               .CLR(), 
               .D(XLXN_3), 
               .Q(MEMfe));
   FDC #( .INIT(1'b0) ) XLXI_3 (.C(XLXN_1), 
               .CLR(), 
               .D(XLXN_4), 
               .Q(MEMc));
   INV  XLXI_4 (.I(MEMA), 
               .O(XLXN_1));
   FDC #( .INIT(1'b0) ) XLXI_6 (.C(XLXN_1), 
               .CLR(), 
               .D(XLXN_5), 
               .Q(CitireStare));
   GND  XLXI_7_4 (.G(D_DUMMY[4]));
   GND  XLXI_7_5 (.G(D_DUMMY[5]));
   GND  XLXI_7_6 (.G(D_DUMMY[6]));
   GND  XLXI_7_7 (.G(D_DUMMY[7]));
   decodif_MUSER_registri  XLXI_8 (.D(D_DUMMY[3:0]), 
                                  .Y0(XLXN_2), 
                                  .Y1(XLXN_3), 
                                  .Y2(XLXN_4), 
                                  .Y3(XLXN_5));
endmodule
`timescale 1ns / 1ps

module reg_stare_MUSER_registri(AchizitieCompleta, 
                                Fifo_gol, 
                                RstStare, 
                                Q);

    input AchizitieCompleta;
    input Fifo_gol;
    input RstStare;
   output [7:0] Q;
   
   wire XLXN_1;
   wire XLXN_2;
   
   FDC #( .INIT(1'b0) ) XLXI_1 (.C(Fifo_gol), 
               .CLR(RstStare), 
               .D(XLXN_2), 
               .Q(Q[0]));
   FDC #( .INIT(1'b0) ) XLXI_2 (.C(AchizitieCompleta), 
               .CLR(RstStare), 
               .D(XLXN_1), 
               .Q(Q[1]));
   VCC  XLXI_3 (.P(XLXN_2));
   VCC  XLXI_5 (.P(XLXN_1));
   GND  XLXI_6_2 (.G(Q[2]));
   GND  XLXI_6_3 (.G(Q[3]));
   GND  XLXI_6_4 (.G(Q[4]));
   GND  XLXI_6_5 (.G(Q[5]));
   GND  XLXI_6_6 (.G(Q[6]));
   GND  XLXI_6_7 (.G(Q[7]));
endmodule
`timescale 1ns / 1ps

module reg_control_MUSER_registri(D, 
                                  MEMC, 
                                  FrontTrig, 
                                  Mod1);

    input [7:0] D;
    input MEMC;
   output FrontTrig;
   output Mod1;
   
   wire XLXN_10;
   wire XLXN_12;
   wire XLXN_14;
   wire XLXN_16;
   wire XLXN_18;
   wire XLXN_20;
   
   FDC #( .INIT(1'b0) ) XLXI_1 (.C(MEMC), 
               .CLR(), 
               .D(D[7]), 
               .Q(XLXN_10));
   FDC #( .INIT(1'b0) ) XLXI_2 (.C(MEMC), 
               .CLR(), 
               .D(D[6]), 
               .Q(XLXN_12));
   FDC #( .INIT(1'b0) ) XLXI_3 (.C(MEMC), 
               .CLR(), 
               .D(D[5]), 
               .Q(XLXN_14));
   FDC #( .INIT(1'b0) ) XLXI_4 (.C(MEMC), 
               .CLR(), 
               .D(D[4]), 
               .Q(XLXN_16));
   FDC #( .INIT(1'b0) ) XLXI_5 (.C(MEMC), 
               .CLR(), 
               .D(D[3]), 
               .Q(XLXN_18));
   FDC #( .INIT(1'b0) ) XLXI_6 (.C(MEMC), 
               .CLR(), 
               .D(D[2]), 
               .Q(XLXN_20));
   FDC #( .INIT(1'b0) ) XLXI_7 (.C(MEMC), 
               .CLR(), 
               .D(D[1]), 
               .Q(FrontTrig));
   FDC #( .INIT(1'b0) ) XLXI_8 (.C(MEMC), 
               .CLR(), 
               .D(D[0]), 
               .Q(Mod1));
   GND  XLXI_9 (.G(XLXN_10));
   GND  XLXI_10 (.G(XLXN_12));
   GND  XLXI_11 (.G(XLXN_14));
   GND  XLXI_12 (.G(XLXN_16));
   GND  XLXI_13 (.G(XLXN_18));
   GND  XLXI_16 (.G(XLXN_20));
endmodule
`timescale 1ns / 1ps

module regrk_MUSER_registri(D, 
                            MEMRK, 
                            Citire_date, 
                            Start_achizitie);

    input [7:0] D;
    input MEMRK;
   output Citire_date;
   output Start_achizitie;
   
   wire XLXN_27;
   wire XLXN_30;
   wire XLXN_31;
   wire XLXN_32;
   wire XLXN_33;
   wire XLXN_34;
   
   FDC #( .INIT(1'b0) ) XLXI_1 (.C(MEMRK), 
               .CLR(), 
               .D(D[7]), 
               .Q(XLXN_27));
...

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