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Charles Clarkeworai ai
Published © GPL3+

GPIO Control on AUP ZU3 with PetaLinux 2022.1

Build a PetaLinux 2022.1 image for the Zynq UltraScale+ AUP ZU3 and control an LED from Linux via sysfs GPIO

IntermediateProtip3 hours29
GPIO Control on AUP ZU3 with PetaLinux 2022.1

Things used in this project

Hardware components

Zynq™ UltraScale+™ XCZU3EG-2SFVC784E
AMD Zynq™ UltraScale+™ XCZU3EG-2SFVC784E
×1
Flash Memory Card, SD Card
Flash Memory Card, SD Card
×1
USB Cable, USB Type C Plug
USB Cable, USB Type C Plug
×1

Software apps and online services

AMD Vivado 2022.1
Ubuntu Core
Ubuntu Core

Story

Read more

Schematics

block diagram and design

Code

led_design_wrapper.v

Verilog
module led_blink101(
    input wire clk,
    output reg led = 1'b0
);

    reg [31:0] counter = 32'd0;

    always @(posedge clk) begin
        if(counter == 32'd50_000_000) begin
            counter <= 32'd0;
            led <= ~led;
        end
        else begin
            counter <= counter + 1'b1;
        end
    end

endmodule

constraint file

Verilog
set_property PACKAGE_PIN AF5 [get_ports led_0]
set_property IOSTANDARD LVCMOS18 [get_ports led_0]
set_property DRIVE 4 [get_ports led_0]

set_property PACKAGE_PIN AH2 [get_ports {led_1_tri_io[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {led_1_tri_io[0]}]
set_property DRIVE 4 [get_ports {led_1_tri_io[0]}]

Credits

Charles Clarke
2 projects • 1 follower
Hardware/ Software Engineer in embedded systems, FPGA design, and circuit development,
worai ai
2 projects • 1 follower
Thanks to worai Ai .

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