Logic Analyzer Project from Digilent Design Contest

The present project consists in a design of a logic analyzer, which can help students and engineers to verify digital hardware, digital communication and software integration. The logic analyzers are usually made with 34 to 136 channels, each channel being a single digital signal, with sampling frequencies up 700 MHz and recording memories up to 64 MB. It does not measure analog details like voltage values, but instead detects levels of logic thresholds.

This design is a simple one allowing recording up to 8 channels, with sample frequency up 12 MHz and recording memories up to 128 B. It fits a relative small and cheap FPGA and can be implemented in house for developing digital and microcontroller application. Acquired date can be transferred to a computer via a serial interface.

General block diagram

The FIFO memory block has a primary element a 128 byte wide memory that temporarily sotes the acquired data from

the inputs. 8 AND gates let the input signals reach the FIFO memory. A 2:1 multiplexer select which data is sentto the Transmission block, either from FIFO memory or from the State register.

The data receiving register is an 11 bit shift register used to store bit by bit the incoming words from the computer. It is initialized to 0 and when clocked by the transmission clock it shifts data until all 11 RS232 incoming bits are stored.

The sampling rate generator allows 12 predefined sampling rates to be selected by software. They are obtained starting from the 12MHz oscillator available on the ARTY board by dividing with different programmable factors (1, 2, 3, 4, 6, 12, 24, 120, 240, 1200, 2400, 12000). The sampling rate is programmed via the RS232 interface from the LabView application. In this block it is included the frequency divider (625) for the baud rate clock, too.

The acquisition block counts the number of bytes that is acquired and stops the process when the preset number is reached (16, 32, 64 or 128). It counts the acquisition clock pulses after the starting conditions is true: trigger event or soft start.

The transmission blockis used to send data over RS232. It uses the same settings as for reception (11 bits with 8 data bits and 2 stopping bits). The data byte is parallel loaded into the shift register and start bit and stop bits are added. Data is shifted on each baud rate clock pulse. The process stops after 11 clocks.

The register blockincludes 5 registers: The address register (reg_adr), the acquisition register (regrk), the Command register (reg_comanda), the Control register (reg_control) and the Status register (reg_stare). The Address register is loaded with the address of the register being written or read. The Acquistion register starts the acquisition by software or clear the data. The Command register programms the number of samples being acquired and the sampling rate. The Control register

programs the trigger slope and mode. The Status register shows informations about the status of the analyser (end of acquistion, reset device and FIFO empty)

Hardware Design

Find all the project details and the source files in the section below the project.