We're Taking a Look at This ECP5-Based Reboot of a Retro Emulation Classic, the SD2SNES

We all know that the hardware community are hardcore about harboring the high score when it comes to retro gaming.

Whether it's button bashing on the on the ArduBoy, or getting rekt on the RetroPie — we love to play on, reliving the memories of yesteryear, and often simpler times that went hand-in-hand with our childhood.

More so than simply loading an emulator though, the hardware scene sides a bit more with some more significant efforts when it comes to getting our screens showing us those simpler graphical games we all seem to recall existing in HD...

So it's no surprise that when a new bit of hardware comes along in the scene, it makes waves.

While it feels like only last month (it was actually November!) were we covering the rather successful efforts that went into reverse engineering the ROM encoding used on the new Nintendo Game & Watch, and since then, our tip line has been tripping off the hook with a triage of hardware tech titbits to investigate.

The latest to grace our news desk is this more modern day reboot on an already successful retro emulation platform, with Sam Littlewood's take on the SD2SNES project — which, as it's name suggest, aims allow you to crack on with loading your library of ROMs directly onto a custom Game Pak cartridge

The result of this hardware effort is a one-shoe-fits-all platform, that for all intents and purposes, speaks the language that the SNES expects to see — appearing as a complete Game Pak, presenting the desired ROM as the console expects to see it — ready to play!

Whereas the original sources for the sd2sens project call into action a Xilinx XC3S400 FPGA, Littlewood looks set to turn the project towards a more open source direction — owing to a re-design of the core card concept, but instead leveraging a Lattice offering for the FPGA; the ECP5 Series: say hello to the sd2nes_ecp5 (a working name, we suppose)!

We can't fault him in his choice of forking the hardware over to a Lattice ECP5 based FPGA instead — moving away from the Xilinx IP, and the often non-trivial licensing agreements involved around its use. Especially when perhaps skirting some hardware areas that have had somewhat frivolous legal threats thrown about them — retro emulation still sometimes attracts modern day litigation... But we digress.

Although this reinvigorated homebrew cartridge clone maintains the very specific board form factor required for it to sit inside existing casings, the differences are very noticeable once you look at the area occupied by the FPGA core, and the footprints for the parts associated with it!

From beautifully raytraced tracks, to beautifully tracked traces

While the original Xilinx part sat in a chonk of a QFP package, the more modern day ECP5 replacement requires a bit more skill in soldering it down to the PCB as it sits packaged inside a ball grid array, with 256 pins stacked into a grid of 0.8mm pitch, some 17mm square.

While not the tightest pitch part on the market, by any stretch, this is still one that requires a bit more than dumb luck when it comes to reflowing in the home lab — and is near impossible for the average hobbyist to inspect. Rework is likely going to be more of a new part than a bodge wire.

However, we see good success in the community — with practice — on similarly spaced pitched parts, such as the ISSI IS66/67WVE4M16E PSRAM (Pseudo-SRAM) packages, seen located to the left of the ECP5. These parts pack 48 connections into a 0.75mm pitch spacing, in a grid of 8x6 - still quite tight, but people seem to have good success with these in home lab reflow setups!

We're big fans of this layout

It's hard not to appreciate the aesthetic of a well laid out board. And when it comes to fanning out all the tracking required for a design as complex as this, you have to appreciate the effort that Littlewood has gone to in creating a layout that looks absolutely sublime!

With the two 64 Mbit PSRAMs located to the left hand side of the Lattice FPGA package, and an additional IS62WV5128EBLL-45BLI 4Mbit, 45ns access time, battery-backed SRAM device routed out towards the top of the image above, we can see that there has been some thought and attention given to the implementation of the memories required to get this project playing all the retro classics.

Precious precious power

As with any FPGA-based hardware, success is often intrinsically linked to a whole range of primary subsystems, not least, the power supplies that pump the voltages required at the currents needed by these power hungry devices!

We can see a capable duo of Texas Instruments TLV62568DBV Switched DC/DC buck converters, configured to independently drop the 5V supplied to the card down to the 3V3 and 1V1 rails required by the ECP5.

We often see switching buck regulators employed in designs where there is a significant current requirement on the rail they regulate down to. They are known to be more efficient than their linear LDO counterparts, but have the trade-off in some slightly more complex layout constraints, to compensate for the currents that have to be carefully managed through the often external magnetics (inductor), so as to achieve the specified operating ratings.

A third voltage regulator, this time a Texas Instruments TLV73325 aptly covers the more meagre 2V5 rail requirements, still supplying a respectable 300mA.

Chiptune music to our ears!

No retro emulation would be complete without the glorious nostalgic feelings felt when our ears hear the faintly (for some) familiar chirps and squawks of the signals generated for our sonic pleasure.

Perhaps far more capable than needed for that purpose, the CS4344 from Cirrus Logic is a 24-bit, 192 kHz Delta Sigma DAC (digital-to-analog converter).

Tasked with taking the PCM serial audio output from the FPGA, it deserializes the data, and generates a pair of modulated analog signals, one for each channel — left and right — both of which are then buffered by a dual, unity-gain op-amp — the TS9222 from STMicroelectronics.

A non-inverting unity gain amplifier, with a gain of one, is more conventionally known as a buffer. Those less familiar with audio might ask why you'd do this...

Instead of simply trying to use the rather weak, high-impedance outputs of the DAC to directly drive a low-impedance load such as a voice coil, the buffers give the low-impedance signal a low-impedance 'boost,' meaning that this design could drive a small set of speakers perhaps, but most certainly a set of headphones!

Sort that pesky CIC with a dinky PIC

We've touched on the architecture of the N64 in a previous article, and like the best console ever (I'll die on that hill...), the SNES employs the CIC protection system that grew into the one used on the N64.

The SuperCIC Key takes care of... 'adjusting' the registered capabilities of the console and Game Pak regional encodings, resulting in the ability to get rekt, region free.

sd2snes_ecp5 Sources

While Littlewood is still porting over the gateware that runs on the original SD2SNES project, things are looking promising. While very much still a work in progress, the intrepid can get to grips with this god-level Game Pak over on the project's GitHub page here.

For more up-to-date... updates, Twitter is usually where it's at. Take a peek at the tweets by giving Littlewood a follow — @samlittlewood.