The Arm-and-RISC-V RVAM16 Aims to Make It Easier to Move From One Embedded Architecture to Another

Designed for the embedded space, RVAM16 can run either RISC-V or Arm Thumb binaries with little performance penalty.

Gareth Halfacree
2 months agoHW101

Researchers at the Chinese National University of Defense Technology have come up with a hardware-based approach to make it easier for people to make the move from the proprietary Arm architecture to the free and open source RISC-V architecture — by building a low-cost embedded processor capable of handling code for both, through hardware binary translation and some clever optimizations.

"The rapid development of ISAs [Instruction Set Architectures] has brought the issue of software compatibility to the forefront in the embedded field," the researchers claim in support of their work. "To address this challenge, one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs. However, due to constraints in cost and performance, the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems."

That optimization is exactly what the team's creation, RVAM16, aims to offer. The processor uses a microarchitecture which offers compatibility with Arm's Thumb ISA and the RISC-V ISA — running code designed for either, without the usual performance penalties of software-based binary translation. The prototype RVAM16 design is, the team claims, able to run RISC-V binaries at full speed, while running Arm Thumb binaries at over 70 per cent of native speed.

"By integrating hardware optimizations in addition to HBT [Hardware Binary Translation], RVAM16 demonstrates a notable 2.73× speed enhancement during the execution of ARM Thumb codes in Dhrystone, and a substantial 4.31× speedup when executing CoreMark," the team claims of its test results. "Furthermore, when running the same ARM Thumb codes, RVAM16 attains 65 per cent of the performance level achieved by the Cortex-M0 processor."

Integrating the team's RVAM16 design into existing Cortex-M0-based processors, the researchers claim, "will not add additional hardware overhead" — and while the current version focuses on the Arm Thumb and RISC-V ISAs, it could be extended in the future to "accommodate any pair of distinct ISAs."

The researchers' work is has been published in the journal Frontiers of Computer Science under open access terms.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
Latest articles
Sponsored articles
Related articles
Latest articles
Read more
Related articles