SiFive Unveils Its Second-Generation RISC-V "Intelligence" Edge AI IP Range

RISC-V pioneer SiFive has announced the second generation of its "intelligence" family, designed for on-device machine learning and artificial intelligence (ML and AI) at the edge: the X160 Gen. 2 and X180 Gen. 2, plus upgraded X280, X390, and XM Gen. 2 designs.

"AI is catalyzing the next era of the RISC-V revolution," claims SiFive chief executive officer Patrick Little on the event of the company's latest launches. "We're seeing strong traction including adoption of the new X100 series by two Tier 1 U.S. semiconductor companies. Our new 2nd Generation Intelligence IP builds on this momentum, adding new features and configurability to accelerate our customers' designs and time to market."

The company's latest launches, which take the form of proprietary IP built atop the free and open source RISC-V instruction set architecture, come a year after the release of the Intelligence XM Series — usable, the company said at the time, as an accelerator for on-device artificial intelligence workloads, but also configurable as the only CPU in a system "incorporating no host CPU."

The second-generation Intelligence family includes an upgraded XM Series Gen. 2, though at the time of writing SiFive had not publicly disclosed full specifications beyond the promise of 16 tera-operations per second (TOPS) of INT8 compute per cluster and an architecture "now heavily tuned for LLMs [Large Language Models]." It has, however, released details regarding its upgraded X280 and X390 Gen. 2 IP, as well as new entry-level designs dubbed the X160 and X180 Gen. 2. These are 32-bit RV32I(E) and 64-bit RV64I implementations designed for energy-efficient edge AI on the Internet of Things (IoT) and supporting up to four cores per cluster, having no memory management unit, and with 128-bit vector length support.

The X280 Gen. 2 sits above these with an RVA23-compliant RISC-V implementation, support for one, two, or four cores per cluster, an SV48 memory management unit, 512-bit vector length support. Finally, the X390 Gen. 2 adds SV57 MMU capabilities and 1024-bit vector length support. All the new models include SiFive Scalar Coprocessor Interface (SSCI) and Vector Coprocessor Interface Extension (VCIX) accelerator control interfaces, and include a loosely-coupled vector pipeline the company claims will avoid memory stalls.

All IP is available to license now, SiFive has confirmed, though with pricing not publicly disclosed, with the first silicon expected in the second quarter of 2026. More information is available on the SiFive website.