SiFive Unveils Its Fourth-Generation "Essential" RISC-V Core Range — From 32-Bit MCUs to 64-Bit CPUs

New processor cores deliver up to a 40 percent energy saving and improved performance, the company claims.

Gareth Halfacree
22 days agoHW101

SiFive, a pioneer in commercialization of the free and open source RISC-V instruction set architecture (ISA), has announced its fourth-generation SiFive Essential processor designs — offering up to a claimed 40 percent reduction in power draw over its third-generation equivalents.

"The best RISC-V embedded solutions just got much better with this fourth generation," boasts SiFive's John Ronco as the company unveiled the refresh at the RISC-V Summit Europe today. "With the benefits of cost-effective flexibility, performance and low power, RISC-V has won the battle for embedded. As legacy ISAs have reduced R&D [Research & Development] and support, we are expanding SiFive's broad portfolio of market leading Essential products and reaffirming our commitment and support for customers in these critical areas of innovation."

The new SiFive Essential range covers the gamut from 32-bit real-time processors for microcontroller and other embedded tasks up to 64-bit application-class processors. On the 32-bit side of the table are the E2, E6, and E7 Gen4 cores, which offer a low-power low-area 2-3 stage single-issue pipeline, more performant eight-stage single-issue pipeline, and high-performance eight-stage dual-issue pipeline respectively.

For 64-bit real-time tasks there's the S2, S6, and S7 Gen4, which are split across the same pipeline designs as above. Finally, the U6 and U7 Gen4 application-class cores are available only in eight-stage single- and dual-issue respectively. All models, the company says, deliver energy savings over their predecessors — delivering, in a best-case scenario, up to a 40 percent reduction in power draw. The new generation also includes improved L1 and L2 cache designs.

The company, which — like its biggest rival, Arm — does not typically produce its own chips in volume but instead licenses the cores to third parties to include in their own designs, has published details of the new cores to its website; pricing has not been publicly disclosed.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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