Renesas Goes In-House, Unveils Its First Home-Brand RISC-V MCU Core — with Silicon Due Early 2024

Embedded hardware specialist Renesas has announced its first fully in-house processor core based on the free and open RISC-V instruction set architecture (ISA) — marking a move away from using third-party core designs, including those from industry giant Arm.

"The increasing popularity of the RISC-V ISA within the semiconductor industry is a boon for innovation. It provides designers with unprecedented flexibility and will slowly but steadily challenge and transform the current landscape of embedded systems," Renesas' Giancarlo Parodi says of the technology behind the company's latest microcontroller. "In the past, Renesas has embraced RISC-V technology introducing 32-bit ASSP devices for voice-control and motor-control built on CPU cores developed by Andes Technology Corp. The exciting next step is the availability of [our] first in-house engineered CPU core."

While Renesas isn't sharing full product details on the parts which will use its in-house core yet, it has confirmed several technical details about the core itself. A block diagram shows a single 32-bit RISC-V core with performance-boosting dynamic branch predictor, a hardware multiplier/divider, a vectored interrupt controller, a stack monitor register, separate instruction and data buses ,and compact JTAG (cJTAG)/JTAG debug capabilities. It has also promised a 3.27 CoreMark per megahertz (CoreMark/MHz) performance level — though at an as-yet unknown clock speed.

"This CPU is suitable for many different application contexts. It can be used as main CPU or to manage an on-chip subsystem or even to be embedded in a specialized ASSP [Application-Specific Standard Product] device," Parodi claims. "Clearly it is very flexible. Second, the implementation is very efficient in terms of silicon area, which helps reduce operating current and leakage current during standby time, besides the obvious effect of smaller cost impact. Third, despite targeting small embedded systems, it provides a surprisingly high level of computational throughput to fulfill the increasingly demanding performance requirement of even deeply embedded applications."

The core makes use of the free and open RISC-V instruction set architecture, along with several of its extensions: Parodi says the core implements the RV32I or RV32E ISA with multiplication (M), atomic access (A), compressed instructions (C), and bit-manipulation (B) extensions. "This is the beauty of the RISC-V ISA concept," Parodi claims, "built from the ground-up to allow the designer to choose which elements to include in the processor, dependent on their target use case, and as a result optimize the trade-off between the resulting power consumption, performance, and silicon footprint."

Renesas says it is sampling silicon with the new core to "select customers" now, with the first commercial chips due to launch in the first quarter of next year. More information is available in Parodi's blog post.