Raspberry Pi Releases Draft Datasheet for the RP1, Its Smart I/O Chip Driving the Raspberry Pi 5

Raspberry Pi has released a draft datasheet for the RP1 input/output (I/O) controller, a major new feature of the upcoming Raspberry Pi 5 and, technically speaking, the first in-house silicon the company ever started designing.

"Raspberry Pi 5 is the most complicated, and expensive, engineering program we’ve ever undertaken at Raspberry Pi, spanning over seven years, and costing on the order of $25 million," claims Raspberry Pi's Eben Upton of the soon-to-launch single-board computer. "It's also our first flagship product to make use of silicon designed in-house here at Raspberry Pi, in the form of the RP1 I/O controller."

That RP1, which despite launching considerably after the also-designed-in-house RP2040 microcontroller on the Raspberry Pi Pico range was actually the first project for Raspberry Pi's in-house chip design team, was added to the Raspberry Pi 5 in order to offload "low-speed" peripherals from the main system-on-chip (SoC) — primarily so that the general-purpose input/output (GPIO) header could remain operating at a 3.3V logic level and enjoy 5V tolerance even while the SoC drops to 1.8V logic.

The RP1 handles the GPIO header, the MIPI Camera Serial Interface and Display Serial Interface (CSI and DSI) ports, the USB 2.0 and 3.0 ports, the gigabit Ethernet port, the analogue video output — no longer available on the 3.5mm AV jack, excised to make room for the twin CSI/DSI ports, but still present on an unpopulated pin header — and other low-speed peripherals required to match the functionality of a Raspberry Pi 4's BCM2711 SoC.

That's only part of the story, though: the draft datasheet released today dives into some of the other features of the RP1 chip, including the presence of two Arm Cortex=M3 processor cores, an eight-channel direct memory access (DMA) controller, three integrated fractional-N phase-locked loops (PLLs), a four-channel 12-bit-resolution analog-to-digital converter (ADC), 64kB of shared static RAM (SRAM), and built-in timebase generators which can be used to pace DMA events or debouncing GPIO.

The RP1 shares what Upton describes as "a certain amount of internal infrastructure" with the RP2040, including a programmable input/output (PIO) block — but the two are very distinct parts.

Even this, though, isn't a complete description of the chip's capabilities. "Unlike our documentation around our microcontroller product RP2040, today’s release doesn’t tell you everything about the RP1 silicon that you might want to know," Upton admits.

"Instead, it's there to help you port an operating system and make use of the features of Raspberry Pi 5. While we are looking at exposing more of the features of RP1, both in software and with further documentation, that’s going to be something you might see a little later on."

The draft RP1 datasheet is available to download from Raspberry Pi now, as a PDF.