PyABV Aims to Add Real-Time and Hardware-Level Verification to PyRTL for Smoother Hardware Design

Researchers from China's National University of Defense Technology (NUDT) have extended PyRTL, the class collection for Python-based register-transfer level (RTL) hardware design, with a new assertion-based verification system dubbed PyABV — aiming to fix bugs before they make it into production while reducing development time.

"Our goal was to bring assertion-based verification directly into the Python workflow," explains corresponding author Tun Li of the team's work, which builds on the open-source PyRTL project's design, simulation, tracing, and testing capabilities, "empowering designers to catch subtle bugs early and reduce turnaround times."

Hardware design comes with a challenge not usually present in software: once the hardware's out there, it's out there — bugs and all. As open-source tooling, including PyRTL, lowers the barrier to entry, increased testing is required to ensure that the hardware works as expected. It's here that PyABV aims to help, delivering assertion-based verification for PyRTL designs.

PyABV is designed to turn assertions into Python objects, making it easier to write temporal checks, while an assertion manager integrates directly into the PyRTL simulator for real-time monitoring — with, admittedly, a 30–40 percent hit to simulation performance, which can be dropped to 20–29 percent with optimization. Assertions can then be translated into a dedicated monitor circuit for hardware-level verification — with an overhead of less than 1.5 percent to the total logic area, the researchers say.

The team's work has been published in the journal Frontiers in Computer Science under closed-access terms; the tool itself is available on Gitee under the same permissive BSD 3-Clause license as PyRTL itself.