OpenHW Group Unveils the Chassis SoC Project for Its RISC-V CORE-V Processor Design

No longer just a processor, the CORE-V Chassis is to be an open hardware system-on-chip when it launches in the second half of next year.

The OpenHW Group has officially unveiled the CORE-V Chassis, a system-on-chip designed around its CORE-V RISC-V processor IP — and it has issued an industry-wide call for participation in its further development.

First unveiled back at the formation of the OpenHW Group in June this year, the CORE-V processor design is based around the Group's CV32E and CV64A IP - the former being a 32-bit embedded-class IP, and the latter a 64-bit application-class IP. Both are variants of core designs from the Parallel Ultra-Low Power (PULP) Platform project, launched by ETH Zurich: RV32IMFCXpulp and RV64GC respectively, which in turn are implementations of the free and open RISC-V instruction set architecture and selected extensions.

The CORE-V Chassis is the logical next step for the OpenHW Group to take: Building on the CORE-V processor IP, the Chassis is a full system-on-chip powered by CORE-V and boasting a full suite of peripherals including 3D and 2D graphics processing hardware, MIPI Display and Camera Serial Interfaces (CSI and DSI), hardware security blocks, USB 2.0 and PCI Express connectivity, a gigabit Ethernet MAC, support for DDR4 and LPDDR4 memory, and multiple SDIO interfaces.

"The CORE-V Chassis project will help validate that serious silicon development is possible utilising the ethos of open-source hardware, IP, and tools," claims OpenHW Group president and chief executive Rick O'Connor. "With the tape out of a functional evaluation SoC during the second half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives."

The SoC design has been created in partnership with founding OpenHW Group member NXP Semiconductor, based on its existing i.MX platform. "NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world class i.MX platform," adds Rob Oshana, NXP vice president for software engineering and OpenHW Group board chair. "We see the CORE-V Chassis project as a natural evolution towards enabling OpenHW Group open-source RISC-V cores for high-performance embedded processing."

While the design of the base CORE-V Chassis is complete, the OpenHW Group has put out a call for industry participation in future multi-core evaluation SoC designs. Those interested are asked to contact O'Connor via email.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire:
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