NXP's MCX N Advanced Chips Promise Low Power Draw, a 30x Boost to Edge AI Performance

Designed for low-power high-performance machine learning at the edge, NXP's latest MCUs are due to sample early next year.

NXP Semiconductors has announced the impending launch of its MCX N Advanced microcontrollers, offering a first look at its in-house neural processing unit (NPU) for high-performance energy-efficient edge artificial intelligence (edge AI) workloads.

"Developers are increasingly looking to push the boundaries of what's possible at the edge as they create new devices that can better anticipate and automate in smart homes, smart factories, and smart cities," claims NXP's Rafael Sotomayor. "This requires advanced MCUs [Microcontroller Units] that are more efficient, simplify edge intelligence, and do all of that securely. As we look to the future of MCUs, the MCX N series delivers the balance between power and performance for tomorrow’s IoT and industrial applications."

The new MCX N Advanced chips form part of the company's MCX porfolio, unveiled back in June, and are designed to sit at the very top end of the performance tables. Both model families — the MCX N94x and MCX N54x — use a heterogeneous multi-core design, which uses a full-fat Arm Cortex-M33 core along with what NXP calls a "streamlined" core designed to handle control functions. Each core can run at up to 150MHz, while machine learning workloads can be offloaded to the integrated NPU — with, the company claims, around a thirtyfold boost in performance compared to running on the CPU cores.

"The multicore design delivers improved system performance and reduced power consumption by enabling smart, efficient distribution of workloads to the analog and digital peripherals," claims NXP's CK Phua. "As a result, the MCUs consume less than 45μA/MHz active current, less than 2.5μA in power down mode with the real-time clock (RTC) enabled and 8kB SRAM retention, and less than 1μA in deep power-down mode with the RTC active and 8kB SRAM."

The two ranges offer equivalent performance, but differ in their target sectors: the N94x chips offer peripherals designed for analog and motor control workloads and comes with 2MB of flash and 512kB of static RAM (SRAM) with Error Correction Code (ECC) protection; the N54x chips focus on high-speed USB with PHY, SD Card, and smart card interfaces for the Internet of Things (IoT) or consumer device use-cases and has 2MB of flash and 512kB of non-ECC SRAM. Both, however, come equipped with NXP's EdgeLock secure subsystem, hardware root-of-trust, secure boot, and cryptographic acceleration.

On the software side, the new chips are compatible with the MCUXpresso software suite, integrated development environments from IAR and Kell, and support "a range of RTOS [Real-Time Operating System] choices." NXP also offers its own development environment for machine learning projects, eIQ, which is claimed to offer easy-to-use tools for training and deployment on the chips' NPU accelerator.

Unfortunately for those eager to try the new parts out, NXP isn't shipping them quite yet: The company is targeting sampling in the first quarter of 2023, and has not yet offered a date for general availability. More information is available on the company's website.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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