Movin' On Up

Moore's Law is dead. Long live Moore's Law! The observation that the number of transistors in an integrated circuit doubles approximately every two years — which has proven to be accurate for decades — is expected to no longer hold true in the near future. A major reason for this change is that we are approaching the physical limits of just how small a transistor can be. Having already arrived at the point where they are just a handful of atomic diameters across, there is little room for further miniaturization.

Moore's Law, now in 3D!

And that could bring technological stagnation in some respects, unless a practical way around this present problem is found. In reality, new innovations are likely to keep forward progress moving right along, with many alternative approaches currently being investigated. One promising approach involves stacking layers of transistors into interconnected 3D structures. This type of arrangement would allow many more transistors to be packed into a given surface area than is possible with conventional 2D chip designs.

There are still some barriers standing in the way of this approach, however. Current manufacturing practices require that bulky silicon wafers serve as a scaffolding on which components are grown. Since each layer in a 3D chip would have such a wafer, the thickness of the chip would rapidly grow, as would communication times between layers. This would negate many of the potential benefits of stacking layers.

But recently, MIT engineers have pioneered a novel approach to chip design that overcomes these limitations, enabling the fabrication of multilayered chips with much better performance. This advancement could ultimately make it possible to produce compact, high-performance chips for devices like laptops and wearables, with capabilities rivaling modern supercomputers.

Planting the seeds of innovation

The researchers previously developed a technique for growing high-quality semiconducting materials, specifically transition-metal dichalcogenides (TMDs), which retain their properties even at atomic scales. While earlier methods required high temperatures that could damage underlying circuitry, the team adapted concepts from metallurgy to grow single-crystalline TMDs at temperatures as low as 380 degrees Celsius. This lower-temperature process involves strategically placing "seed" materials at the edges of silicon dioxide masks, where nucleation requires less heat, enabling the growth of high-quality layers on prefabricated transistor circuits.

Using this refined method, the team successfully fabricated a multilayered chip with alternating layers of two different TMDs — molybdenum disulfide and tungsten diselenide — representing the n-type and p-type transistors essential for logic operations. By eliminating the need for intermediate silicon wafers, the approach significantly increases the density of semiconducting elements and simplifies the manufacturing process. The resulting 3D chips could integrate logic and memory layers seamlessly, drastically improving computation speed and efficiency.

At present, the team is working to commercialize their technology. As it scales, it holds the potential to revolutionize the semiconductor industry, paving the way for ultra-fast, energy-efficient artificial intelligence systems and unprecedented levels of computational performance. Perhaps Moore's Law will be seen as too conservative in the future.