Morten Petersen's Ripes 2.0.0 Offers Interactive Visualization and Simulation of RISC-V Processors

Ripes lets you code your own RISC-V processor, then see the program run in a fully interactive simulation.

Gareth Halfacree
4 years agoHW101

Morten Petersen has announced the release of Ripes 2.0.0, the latest version of his graphical processor simulator and assembly code editor for the free and open RISC-V instruction set architecture (ISA).

"This update represents a complete overhaul of the simulator and visualization infrastructure as well as a revamp of the user interface," Petersen claims of the Ripes project's second ever major-version release. "The update aims to address many of the feature requests I've received since first announcing the Ripes simulator on the RISC-V Teach mailing list a couple of years ago.

"Some of the major new features includes: Multiple processor models - Single cycle, 5 Stage without hazard detection/resolution and forwarding, 5 Stage without hazard detection/resolution, [and] 5-stage Pipeline; Reversible simulation; Interactive visualisations."

Designed primarily for education, Ripes allows for assembly-level code to be created then run through a simulator with an interactive display which - in its latest incarnation - includes an overview of all registers, instruction memory, and output along with interactive visualisations of the data path through the processor. The result, as Petersen points out: "Given that Ripes simulates the entire datapath of a processor, it is possible to investigate the value of any signal, at any point in time."

The latest release of Ripes can always be found on Petersen's GitHub repository, along with the source code under the permissive MIT Licence.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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