To create programmable logic kernels, the Vitis V++ Compiler is capable of compiling OpenCL, C/C++ and RTL in to Xilinx Object (.xo) file and then linking these into the Xilinx binary (.xclbin) for the programmable logic.
When combined with the host development flow, this lets us perform a top down acceleration of our application using Vitis IDE.
However, looking at the FPGA Binary Creation Flow we can also create acceleration kernels from the bottom up using HLS or RTL.
Such a bottom up flow allows us to focus on complex kernel algorithms, verifying its performance and ensuring the optimization for programmable logic implementation provide the best implementation.
This approach also works better with a team approach and enables the creation of acceleration kernel libraries which can be used across multiple projects. One additional advantage is the optimizations applied for the programmable logic implementation reside in the .xo file removing the need for optimization each time the algorithm is used.
We can implement this flow using Vivado HLS, though with Vitis we get Vitis HLS which is included in the bin directory of the Vitis installation.
There are also a number of Vitis HLS tutorial projects available on Xilinx GitHub
These tutorials cover aspects such as algorithm development, coding styles, interfacing and memory architectures — everything we need to start developing effective kernels.
If we are using Windows, we can call the Vitis HLS from the Xilinx Software Command Line Tool by entering the command:
In our Linux system, after we have run the setup script settings64.sh in the installation directory we can use the same command from a terminal window.
This will lead to Vitis HLS loading and the welcome page.
We can use the examples by cloning or downloading a ZIP file from GitHub. If we explore a library, we will find the source code and TCL files that support the example.
We can run these examples from either a Linux terminal or XSCT by changing into the directory and ruining the command:
vitis_hls -f run_hls.tcl
This will run the project in the command line mode and synthesize the project.
Once the command line project has finished you will see a new directory which contains the solution and the project file.
To explore the design, we can use the Vitis GUI if already open to navigate to the example project directory. Alternatively from XSCT we can open the GUI using:
Once the GUI is open you will see an eclipse based workspace which looks similar to Vivado HLS, however there are subtle differences.
In the GUI, we can explore the Synthesis report, debug the application and analyse the implementation for programmable logic implementation.
By default the implementation will be set to generate a RTL based solution, yet if we wish to implement the accelerated function in Vitis using the bottom up flow and generate a Xilinx Object.
We can check the option Vitis Bottom Up Flow under the solution settings.
When we next perform the Synthesis we will see not only the Verilog and VHDL implementations but also the kernel which will contains a XML file of the kernel description.
Once we are happy with the performance of the algorithm we can then export the Xilinx Object. In this case as we have used a simple example from the tutorial projects it is pretty simple and small.
From the export RTL dialog, select the Vitis kernel option in place of the normal Vivado IP.
This will export the Xilinx Object to the output location.
Now we are able to take that XO file and include it in one or several of our Vitis designs. Of course, we can also export the IP into Vivado if we require a hardware implementation.
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