MicroZed Chronicles: Spartan-7 and the SP701 Board

Get up and running with Xilinx's SP701 board featuring a Spartan-7 XC7S100 FPGA.

It has been a little while since we looked at a new development board. I recently received an SP701 board which contains the largest Spartan-7 devices: the XC7S100.

In addition to the Spartan-7 FPGA on the SP701, we also have the following:

  • DDR - 4 Gb of DDR3L SDRAM
  • QSPI - 1 Gb non-volatile storage
  • 6 Pmod
  • Dual Ethernet - industrial networking
  • FMC - LP FMC connector
  • HDMI - ADV7511 supporting HDMI 1.4
  • MIPI CSI and DSI interfaces

This makes the SP701 a very powerful development board for Spartan-7-based solutions.

I have plans for the SP701 board based on its MIPI interfaces. However, to get started with the SP701, I wanted to create a simple application that uses a MicroBlaze processor to interface to several different Pmod types, while running the application from DDR3L SDRAM.

This will allow me to get the MicroBlaze solution I need for the MIPI project up and running, and test it out the DDR3L interface is correct.

To get started with the SP701 board, the first thing I needed to do is to download the XDC constraints from the SP701 Xilinx page.

The second thing is to download the Digilent Vivado Library as this contains several Pmod drivers for Vivado and Vitis.

With the necessary pre-requisites in place, I was able to create a new project. When it comes to targeting the SP701 board, its configuration information is built into Vivado so we can select it from the boards tab.

With the project created, the next step is to create a block diagram project and add in the DDR memory.

We can drag the DDR3 SRAM from the board tab on to the block diagram. This will configure the Memory Interface Generator (MIG) for the exact DDR3L fitted to the SP701.

This will be clocked by the 200 MHz system reference clock provided by the on board clock generator.

Use the + icon to add in a MicroBlaze processor, drag and drop the UART from the board tab along with adding in the Pmod Nav, GPS, ALS, AD2 and NAV IP blocks.

Using the same approach as for the UART and DDR3, drag and drop the LED driver on to the diagram.

Run the block automation, leaving the parameters unchanged.

Once the block automation is completed, run the connection automation to connect together the IP blocks.

To complete the build, make the Pmod ports external and name them PMOD1 to PMOD5.

The XDC file below can be used to build the bitstream. Once this is built, export the XSA and open Vitis.

set_property PACKAGE_PIN C13      [get_ports "PMOD1_pin1_io"] ;# Bank  16 VCCO - VCCO_3V3 - IO_L10N_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L10N_T1_16
set_property PACKAGE_PIN D14 [get_ports "PMOD1_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L15N_T2_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L15N_T2_DQS_16
set_property PACKAGE_PIN B14 [get_ports "PMOD1_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L6P_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L6P_T0_16
set_property PACKAGE_PIN B15 [get_ports "PMOD1_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L6N_T0_VREF_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L6N_T0_VREF_16
set_property PACKAGE_PIN A13 [get_ports "PMOD1_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_0_16
set_property PACKAGE_PIN C14 [get_ports "PMOD1_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L11P_T1_SRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L11P_T1_SRCC_16
set_property PACKAGE_PIN A14 [get_ports "PMOD1_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L1P_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L1P_T0_16
set_property PACKAGE_PIN A15 [get_ports "PMOD1_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L1N_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L1N_T0_16
set_property PACKAGE_PIN D16 [get_ports "PMOD2_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L16N_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L16N_T2_16
set_property PACKAGE_PIN E18 [get_ports "PMOD2_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L20N_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L20N_T3_16
set_property PACKAGE_PIN E20 [get_ports "PMOD2_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L21P_T3_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L21P_T3_DQS_16
set_property PACKAGE_PIN F19 [get_ports "PMOD2_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L24P_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L24P_T3_16
set_property PACKAGE_PIN C17 [get_ports "PMOD2_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L12P_T1_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L12P_T1_MRCC_16
set_property PACKAGE_PIN D19 [get_ports "PMOD2_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L17N_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L17N_T2_16
set_property PACKAGE_PIN E16 [get_ports "PMOD2_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L19N_T3_VREF_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L19N_T3_VREF_16
set_property PACKAGE_PIN G19 [get_ports "PMOD2_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_25_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD2_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_25_16
set_property PACKAGE_PIN C22 [get_ports "PMOD3_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L14P_T2_SRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L14P_T2_SRCC_16
set_property PACKAGE_PIN E21 [get_ports "PMOD3_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L21N_T3_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L21N_T3_DQS_16
set_property PACKAGE_PIN F20 [get_ports "PMOD3_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L24N_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L24N_T3_16
set_property PACKAGE_PIN D18 [get_ports "PMOD3_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L17P_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L17P_T2_16
set_property PACKAGE_PIN D21 [get_ports "PMOD3_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L18N_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L18N_T2_16
set_property PACKAGE_PIN D20 [get_ports "PMOD3_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L18P_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L18P_T2_16
set_property PACKAGE_PIN C19 [get_ports "PMOD3_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L13P_T2_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L13P_T2_MRCC_16
set_property PACKAGE_PIN E17 [get_ports "PMOD3_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L20P_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD3_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L20P_T3_16
set_property PACKAGE_PIN A23 [get_ports "PMOD4_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L4N_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L4N_T0_16
set_property PACKAGE_PIN A24 [get_ports "PMOD4_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L5P_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L5P_T0_16
set_property PACKAGE_PIN B24 [get_ports "PMOD4_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L10P_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L10P_T1_16
set_property PACKAGE_PIN C23 [get_ports "PMOD4_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L14N_T2_SRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L14N_T2_SRCC_16
set_property PACKAGE_PIN B22 [get_ports "PMOD4_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L9N_T1_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L9N_T1_DQS_16
set_property PACKAGE_PIN A25 [get_ports "PMOD4_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L5N_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L5N_T0_16
set_property PACKAGE_PIN C24 [get_ports "PMOD4_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L15P_T2_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L15P_T2_DQS_16
set_property PACKAGE_PIN C21 [get_ports "PMOD4_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L13N_T2_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD4_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L13N_T2_MRCC_16
set_property PACKAGE_PIN A18 [get_ports "PMOD5_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L2N_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin1_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L2N_T0_16
set_property PACKAGE_PIN A19 [get_ports "PMOD5_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L3P_T0_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin2_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L3P_T0_DQS_16
set_property PACKAGE_PIN A20 [get_ports "PMOD5_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L3N_T0_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin3_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L3N_T0_DQS_16
set_property PACKAGE_PIN B21 [get_ports "PMOD5_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L9P_T1_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin4_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L9P_T1_DQS_16
set_property PACKAGE_PIN C18 [get_ports "PMOD5_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L12N_T1_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin7_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L12N_T1_MRCC_16
set_property PACKAGE_PIN B19 [get_ports "PMOD5_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L8P_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin8_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L8P_T1_16
set_property PACKAGE_PIN B20 [get_ports "PMOD5_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L8N_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin9_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L8N_T1_16
set_property PACKAGE_PIN A22 [get_ports "PMOD5_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L4P_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports "PMOD5_pin10_io"] ;# Bank 16 VCCO - VCCO_3V3 - IO_L4P_T0_16

Once the bitstream is completed, open Vitis and select a workspace to work inside.

Create a new application project with the name of mem_test.

Select the XSA we just exported from Vivado.

For the template application, select memory tests. This will enable us to test the DDR3L memory.

This will create a platform project and a memory test system application project

Exploring the memory_config_g.c file will show the memory types to be tested in the application.

Running the application on the MicroBlaze should result in the output below showing the memory test has passed.

This means we can be confident the DDR3L memory is correctly set up in out design.

The next step is to start using the Pmod drivers to create a simple application. You will be able to see the Pmod IP drivers included on the platform and click on the modify BSP settings.

The drivers tab will show the Pmod APIs included in the BSP, which we will use these next time to create a simple application.

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.

Adam Taylor
Adam Taylor is an expert in design and development of embedded systems and FPGA’s for several end applications (Space, Defense, Automotive)
Related articles
Sponsored articles
Related articles