To get started with the MicroZed Chronicles for the new year, I thought we would take a look at one of the more complex boards I have, the ZCU111 and the RFSoC.
More specifically, we are going to look at the Avnet RFSoC Explorer. The Avnet RFSoC Explorer enables us to control the RF mixed signal converters in the RFSoC on the ZCU111 using MATLAB.
Coupled with a Qorvo RF front end we can rapidly prototype RFSoC solutions directly from MATLAB, pretty neat really!
To get started with the RFSoC Explorer prototyping, we first need to set up the Avnet RFSoC Explorer in MATLAB (We need MATLAB version 2019B).
Once MATLAB has started from the add-on button, we can search for and install the Avnet RFSoC Explorer add-on.
To be able to access and control the hardware on the ZCU111, we need to also install the Communications Toolbox-Support Package for Xilinx Zynq-based radio.
Again. this can be found under the Add-On Explorer by searching for communication toolbox support.
Select the appropriate toolbox and select install.
With the MATLAB environment set up, we are now ready to configure the hardware and start working with the Avnet RFSoC Explorer.
The first thing we need to do is connect the Qorvo 2x2 RF front end to the ZCU111 and download the Linux image for the RFSoC to be able to work with Avnet RF Explorer.
We can download the image for the SD Card here. Copy these files to your SD card and boot the ZCU111.
All communication between the ZCU111 and MATLAB uses a gigabit Ethernet link.
As such we need to know the IP address, therefore using a serial terminal issue the ifconfig command to determine the IP address.
We can also use the serial terminal to control the Qorvo RF front end, which enables us to control the low noise amplifier, power amplifier and attenuators.
The program we use to do this is started by typing, Qorvo in the serial terminal.
To prepare the Qorvo RF front end for use, we need to download the default configuration using this application (Select V in the Qorvo application).
We are now ready to start the Avnet RFSoC Explorer in MATLAB, from the APPS menu select Avnet RFSoC Explorer.
This will launch the Avnet RFSoC Explorer.
From the main tab, we can enable and configure the DAC and ADC subsystem as we desire for our testing. Each DAC or ADC tile can be enabled by clicking the on/off button. This will open a new tab for the tile configuration in detail.
For this simple example, we are going to configure the ADC to sample at 1081.344 MSPS and set ADC complex mixer to -1842 MHz. This will mean a signal present at 1843 MHz will appear be located at 1 MHz in the output spectrum.
With the ADC configured, we need to generate a tone using the DACs.
To do this, I enabled Tile 1 DAC and configured a sampling rate of 6389.76 MHz and the complex mixer for a center-frequency of 1842 MHz.
We can then use the ADC tile to capture and display samples from the DAC. You will notice the spectrum shows the CW tone at 1MHz as expected however, the amplitude is low.
Using the Qorvo application in the serial terminal, we can control the settings on the Digital Pre Distortion measurement path we are monitoring and TX attenuator until we receive a 0 dBFS signal at the ADC, increasing the power beyond this may damage the RF-ADC.
The great thing about the RFSoC Explorer is we can generate signals in MATLAB and then apply them to the RFSoC.
Let's wrap up looking at a LTE-4G signal on the DAC tile setting from the signal source select wireless waveform.
This will open up the wireless waveform generator. Using this waveform generator, we can create a LTE-4G signal and transmit and receive it via the RFSoC.
Capturing the signal again using the ADC will show the input spectrum and the LTE signal; however, there is saturation of the PA which is causing some distortion.
By adjusting the attenuation at the power amplifier we can clean up this signal.
It is pretty easy to generate waveforms and verify the performance in the RFSoC using the RFSoC explorer.
I am going to be using the Avnet RFSoC Explorer for several projects I am working on at the moment!
See My FPGA / SoC Projects: Adam Taylor on Hackster.io
Get the Code: ATaylorCEngFIET (Adam Taylor)
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