In last week’s blog, we examined the Pynq framework for the ZCU111 and its RFSoC.
To be able to effectively leverage the Pynq framework on the ZCU111, we need to be able to create overlays for the RFSoC which utilize the giga-sample DACs and ADCs.
So, over several upcoming blogs we are going to take a look at how we can get started developing our own RFSoC design, leading to the creation of a Pynq RFSoC overlay. It will take a few articles, so I will inter space RFSoC posts with other topics.
Let’s start with an in-depth look at the Data Converter itself, after all it is the heart of the RFSoC.
The Data Converter is represented in the programmable logic (PL) design as a tile. This tile includes the ADCs and DACs along with all the necessary logic for control and status reporting.
As you can see at a conceptual level, the RF Data Converter uses AXI streams for transmission data (DAC Path) or received data (ADC Path), while control, configuration and status reporting is achieved using AXI Lite.
Of course, the analogue inputs and outputs are dedicated pins on the RFSoC package.
The RFSoC also has a number of other dedicated pins, including ADC and DAC sampling clocks (ADC_CLK DAC_CLK) and an external system synchronisation input (SYSREF).
When it comes to providing the sampling clocks for the DACs and ADCs, we have two options.
- Provide the sampling frequency directly, e.g. for a 2GSPS the ADC/DAC clock would be 2000 MHz.
- Provide a reference clock to the PLL within the RF Data Converter tile, which then generates the appropriate sample clock.
The PLL can be enabled and configured in the Data Converter customization dialog.
When it comes to implementing the RF Data Converter in our PL design, we instantiate the RF Data Converter by typing RF in the add IP dialog in IP Integrator.
Once the RF Data Converter has been added to the IP Integrator block design, we can customize it for our application.
Using this customization tab, we can enable and configure the DAC and ADC as we desire.
This includes configuration of the sample rate, digital and analogue output format (Real or I&Q), decimation / interpolation modes, mixer configurations (Real->Real, Real->IQ, IQ->IQ, IQ->Real), Nyquist zone, and calibration mode.
With this configuration dialog, we can also select the clocking strategy for the ADC / DAC clock. This determines if the dedicated ADC/DAC clock input provides either a sample clock or a PLL reference clock.
To understand more about the RF Data Converters, prior to implementation we can open RF Data Converter reference designs using Vivado.
We do this by clicking on the RF Data Converter block within the design tab and selecting Open IP Example Design.
This will create a new Vivado project containing the example design. In the block diagrams below, I created separate example projects which contained either one ADC or one DAC.
Using these example projects, we can then simulate with our preferred simulation tool. I used Vivado Simulator for this blog. With this approach, we can explore the solution space and configuration of the ADC/DAC before implementation.
In the next blog on the RFSoC, we will examine in greater detail the software architecture necessary to control the RF Data Converters in our application.
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