The RFSoC is one of the devices I have wanted to get my hands on, ever since its announcement. So I was very excited to find a ZCU111 RFSoC development board waiting for me when I recently returned from Linaro Connect.
For those unfamiliar with the RFSoC, it combines the Zynq MPSoC PS and PL with multi-gigasample per second DACs and ADCs — making the RFSoC ideal for a number of applications including communications, RADAR, 5G, DOCSIS, SatCom, etc.
The ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVG1517E RFSoC that provides:
- Eight 4 GSPS 12-bit RF ADC
- Eight 6.5 GSPS 14-bit RF DAC
- Eight Soft Decision Forward Error Correction (SD-FEC)
To enable users to prototype a range of solutions, the ZCU111 also offers a range of interfacing capabilities including Ethernet, SFP28 Cages, SATA, USB3, and high pin count FMC for additional flexibility. Of course, with a device like the RFSoC moving data on and off the board at high speed is critical, hence the range of different high speed connectivity options.
As the RFSoC enables complex single device solutions, the ZCU111 also features two banks of DDR 4, each bank is 4GB. One bank is connected to the PS, while the second is connected to the PL. The 4GB connected to the PS enables operating systems such as Linux to be used to implement higher levels of the applications, e.g. communication, system management, security, and adaption. While the DDR bank connected to the PL can be used in the signal processing path.
The most important element of the ZCU111, though, is how we connect the RF ADCs and RF DACs within the RFSoC to the outside world. This is made possible through two RFMC connectors — one connector provides RF output, the other RF inputs.
Rather helpfully, the ZCU111 is provided with a Balun board which connects to both of these interfaces. Along with providing the Baluns that convert between differential and single ended signaling, this board is equipped with multiple SMA connectors for RF input and output.
Once I had unpacked the board, I read the supporting information online about the ZCU111 and its configuration. The first thing I wanted to do was a loop back test using two DACs to stimulate two ADCs. We can do this physically with the Balun board, and rather useful, the ZCU111 also comes with a Targeted Reference Design (TRD) which enables us to configure the RFSoC ADCs and DACs to do just that (and more as we will see in future blogs).
To get the example up and running, we need to create an SD card which contains the TRD image and also install the RF Data Converter Evaluation User Interface GUI on a PC. This GUI allows us to communicate with the RFSoC over Ethernet and configure both clocking and the DAC and ADC tiles. This GUI also lets us generate simple signals and examine the received spectrum, exactly what we want.
For this simple example using the GUI, I configured the RFSoC to use two of the DACs available in DAC tile one for signal generation. I also configured the RFSoC to use the ADCs available in ADC tile one to receive the generated signals.
The first step in doing this is to correctly configure the DACs as follows:
Sample clock = 6389.76 MHz
Crossbar I & Q, Interpolation x8, Decoder Mode High Linearity and Mixer Frequency of 1500 MHz.
The second step is to configure the ADC in tile one, which can be done as follows:
Sample Clock = 3194.88 MHz
Decimation x4, Mixer Frequency -1200 MHz
With both the ADC and DAC configured, the next step is to create stimulus for the ADC using the DAC.
We do this on the signal generation tab, which is available for each DAC. In this tab, we can enter a Center Frequency. The image below shows a CF of 150 MHz.
For this example, I used Center Frequencies of 150 MHz and 200 MHz.
With the stimulus being generated, I was then able to monitor the ADC signals using the acquisition function. The acquisition function allows the received signal to be examined in either the time or frequency domain.
For most applications, the frequency domain view is the most suitable and provides the most information on the converter and system performance.
With both DACs generating signals with CF at 150 MHz and 200 MHz, the plots below show the received data.
These plots show the base band signal at 100 MHz and 150 MHz. These are the frequencies as would be expected as the lower side band is reduced by 1200 MHz in the ADC channel.
At the DAC output, this lower side band would be at either 1300 MHz or 1350 MHz depending upon the setting of Center Frequency.
As you can see, both ADC channels capture the signal at the expected location in the received frequency domain.
If you want to see the example in action I took a simple video while setting up the examples.
This is a really great board and device and I cannot wait to do more with it over the coming weeks and months.
See My FPGA / SoC Projects: Adam Taylor on Hackster.io
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