Ken Shirriff Turns Lumafield's CT Scanning Tech on Intel's Classic 386

Noted reverse engineer Ken Shirriff has peered deeper into the 386 processor than anyone outside Intel, courtesy of a 3D computed tomography (CT) scan performed by Lumafield — revealing the complexity that lies within the package.

"Intel released the 386 processor in 1985, the first 32-bit chip in the x86 line," Shirriff explains. "This chip was packaged in a ceramic square with 132 gold-plated pins protruding from the underside, fitting into a socket on the motherboard. While this package may seem boring, a lot more is going on inside it than you might expect. Lumafield performed a 3D CT scan of the chip for me, revealing six layers of complex wiring hidden inside the ceramic package. Moreover, the chip has nearly invisible metal wires connected to the sides of the package, the spikes below. The scan also revealed that the 386 has two separate power and ground networks: one for I/O [Input/Output] and one for the CPU's logic."

The 80386, later i386, was Intel's third-generation entry in the x86 range, launched in October 1985 and not formally discontinued until September 2007. Building upon the 286, the 386 offered a longer pipeline and a 32-bit architecture with three operating mode: real mode, protected mode, and virtual mode — the latter allowing the user to run real mode programs in a protected environment, if compatible.

When reverse engineers look at integrated circuits, it's normally the silicon die at their heart that is of interest — the part that contains all the transistors that make the thing tick. The package in which it's installed is usually of little concern, with everything from the bond wires outwards being ignored — but Lumafield's 3D scan allowed Shirriff to peer beyond the de-encapsulated die and see how the tiny bond wires make it to the chunky pins mating the chip to its motherboard.

Studying the scan Shirriff discovered an unexpected number of connectivity layers, comprised of six power planes across two distinct power networks plus the signal layers. "The pins are connected to the package's shelf pads through metal traces," Shirriff notes, "spectacularly colored in the CT scan. (These traces are surprisingly wide and free-form; I expected narrower traces to reduce capacitance.) Bond wires connect the shelf pads to the bond pads on the silicon die."

"What surprised me most about the scans," Shirriff adds, "was seeing wires that stick out to the sides of the package. These wires are used during manufacturing when the pins are electroplated with gold. In order to electroplate the pins, each pin must be connected to a negative voltage so it can function as a cathode. This is accomplished by giving each pin a separate wire that goes to the edge of the package."

The full write-up is available on Shirriff's blog, along with an interactive graphic showing different layers from the scan.