ET-SoC-1 Chip with More Than 1,000 RISC-V Cores Aimed at Accelerating Machine Learning

Esperanto ET-SoC-1 64-bit with 100X better energy efficiency, therefore reducing the energy costs in data centers.

Abhishek Jadhav
10 months agoMachine Learning & AI
Chip with 1089 ET-Minions and four ET-Maxions in 7nm (📷: hpcwire)

At the RISC-V Summit 2020, Art Swift, CEO of Esperanto Technologies, announced the development of a chip based on the open source RISC-V architecture with more than 1,000 cores. The chip targeted at accelerating machine learning applications, becoming the first of the AI processors family for Esperanto Technologies.

The chip Esperanto ET-SoC-1 64-bit, contains more than "1,000+ RISC-V custom cores with 23.8B transistors using TSMC 7nm manufacturing nodes." It is designed to be power efficient, showing almost 100X better energy efficiency on key workloads. Due to this, there is a huge decrease in the energy costs in data centers.

The manufacturer claims the chips have up to 50X better performance on key workloads like recommendation networks and up to 30X for image classification. The important point to note here is that the performance of ET-SoC-1 chip is based on the emulation.

The chip has two types of general-purpose 64-bit cores, namely, the ET-Maxion (superscalar out-of-order core) and the ET-Minion (in-order multithreaded core). According to the design, there will be only four cores of ET-Maxion per chip, while more than 1,000 cores of ET-Minion per chip in 7nm technology.

Additionally, the chips support LPDDR4x DRAM with up to 32GB DRAM, 137GB/sec memory bandwidth, and a 256-bit wide interface.

Swift says there can be up to six ET-SoC-1 chips on a Glacier Point v2 card. This one card has around 6558 RISC-V Cores, 192 GB of DRAM, and 822 GB/s DRAM bandwidth.

The Esperanto’s tiled AI solution is meant "to scale from hundreds to thousands of CPU cores," which makes it interesting to see more RISC-V based cores in future from the company.

Abhishek Jadhav
Abhishek Jadhav is an engineering student, freelance tech writer, RISC-V Ambassador, and leader of the Open Hardware Developer Community.
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