EdgeQ Adopts Andes RISC-V-Based Cores for Upcoming Modems

EdgeQ to use Andes RISC-V core to develop an open and programmable 5G platform with integrated AI.

To continue the momentum of RISC-V architecture and its implementation in the AI and 5G space, Andes Technology has announced that EdgeQ will be using Andes RISC-V core to develop an open and programmable 5G platform with integrated AI. EdgeQ, a 5G cellular startup, has planned to implement its own custom instructions to provide high-performance and best-in-class features.

“We are excited and proud to have our RISC-V AndesCore incorporated into EdgeQ’s ambitious program to develop their 5G and AI silicon platform,” said Frankwell Lin, Andes Technology President. “Using Andes ACE to easily extend the RISC-V ISA for custom requirements offers EdgeQ’s design teams the freedom to more precisely configure the performance, power consumption, and die area of their final silicon.”

EdgeQ is known for its 5G and AI-based technology for designing a base station on a chip with reduced complexity. The RISC-V-based base station on a chip saves up to 50% of the total cost of ownership. Additionally, it enables flexible topologies based on ORAN 7.x splits of radio unit, distributed unit, or central unit.

One of the major advantages of using RISC-V based open instruction set architecture in EdgeQ is that the team can now focus on writing custom extensions for their new applications to improve performance. With EdgeQ adding to the long list of RISC-V adopted startups for their new hardware designs, it has set a new standard in the wireless infrastructure space.

Abhishek Jadhav
Abhishek Jadhav is an engineering student, freelance tech writer, RISC-V Ambassador, and leader of the Open Hardware Developer Community.
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