Canaan Announces Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU

The successor to the K210, the new K510 promises twice the clock speed, three times the NPU performance, and an extra core for DSP work.

Canaan has announced the sampling of a RISC-V chip designed specifically for edge AI workloads, at the World Artificial Intelligence Conference 2021: the Kendryte K510.

"The Kendryte K510 chip is the result of two years of work by our R&D team to further innovative and optimize our core chip architecture," Canaan chair and chief executive officer Nangeng Zhang claims of his company's latest announcement. "With upgraded machine vision and improved programming flexibility, the Kendryte K510 can better address the demands of mid- to high-end application scenarios."

"Looking ahead, we expect this chip to be a highly attractive choice for developers as it enables them to deliver more intelligent product experiences to their users."

The earlier Kendryte K210, a system-on-chip design which included a dual-core 400MHz 64-bit RISC-V processor with hardware floating-point unit alongside a custom neural-network acceleration coprocessor, proved popular: It can be found at the heart of everything from Raspberry Pi add-ons to binocular computer vision boards, all-in-one Internet of Things (IoT) development kits, handhelds, and educational robots.

The new K510 is designed to offer upgrades across the board. The dual-core RISC-V processor now offers three cores, split into a dual-core block running at 800MHz and a single-core block acting as a digital signal processor (DSP). The new coprocessor, meanwhile, boosts compute throughput to a claimed 3 trillion operations per second (TOPS) across neural network, fast Fourier transform (FFT), and voice activity detection (VAD) workloads, and there's 1.5MB of static RAM (SRAM) split across 1MB and 512kB blocks with LPDDR3/4 support for system RAM.

The chip also includes USB 2.0 OTG support, gigabit Ethernet, MIPI CSI and DVP camera interfaces, an H.264 video encoder capable of 1080p60, MIPI DSI and BT1120 display options, AES and SHA acceleration with a true random number generator, and a range of peripherals including four UARTs, AUDIF, three SPI buses, three SDIO buses, and both system and peripheral direct-memory access.

While Zhang announced the part at the conference, though, the company isn't quite ready to begin shipping: Instead, it promises to sample the component this year, with general availability β€” and the public release of a software development kit β€” to follow.

The part has not yet made it to the company's English language website.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire:
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